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DS21Q50 Quad E1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21Q50 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1 22AWG (0.6mm) twisted-pair cables from 0km to over 2km in length. The device can generate the necessary G.703 waveshapes for both 75W coax and 120W twisted-pair cables. The on-board jitter attenuators (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framers locate the frame and multiframe boundaries and monitor the data streams for alarms. The device contains a set of internal registers, from which the user can access and control the operation of the unit by the parallel control port or serial port. The device fully meets all the latest E1 specifications including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431 ETS 300 011, ETS 300 233, and ETS 300 166 as well as CTR12 and CTR4.
FEATURES
Four Complete E1 (CEPT) PCM-30/ISDN-PRI Transceivers Long-Haul and Short-Haul Line Interfaces 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Frames to FAS, CAS, CCS, and CRC4 Formats 4MHz/8MHz/16MHz Clock Synthesizer Flexible System Clock with Automatic Source Switching on Loss-of-Clock Source Two-Frame Elastic-Store Slip Buffer on the Receive Side Interleaving PCM Bus Operation Up to 16.384MHz Configurable Parallel and Serial Port Operation Detects and Generates Remote and AIS Alarms Fully Independent Transmit and Receive Functionality Four Separate Loopback Functions PRBS Generation/Detection/Error Counting 3.3V Low-Power CMOS Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits Eight Additional User-Configurable Output Pins 100-Pin, 14mm x 14mmLQFP Package
APPLICATIONS
DSLAMs Routers IMA and WAN Equipment
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
PART DS21Q50L DS21Q50LN TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 100 LQFP (14mm) 100 LQFP (14mm)
DS21Q50
100 1
LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 013004
DS21Q50
TABLE OF CONTENTS
1. 2. INTRODUCTION ...............................................................................................................................6 PIN DESCRIPTION............................................................................................................................9 2.1 PIN FUNCTION DESCRIPTION.........................................................................................................15
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 System (Backplane) Interface Pins .......................................................................................................15 Alternate Jitter Attenuator ....................................................................................................................16 Clock Synthesizer..................................................................................................................................16 Parallel Port Control Pins....................................................................................................................16 Serial Port Control Pins .......................................................................................................................17 Line Interface Pins................................................................................................................................18 Supply Pins ...........................................................................................................................................18
3.
HOST INTERFACE PORT..............................................................................................................20 3.1 PARALLEL PORT OPERATION ........................................................................................................20 3.2 SERIAL PORT OPERATION .............................................................................................................20 3.3 REGISTER MAP .............................................................................................................................23 CONTROL, ID, AND TEST REGISTERS.....................................................................................24 4.1 POWER-UP SEQUENCE ..................................................................................................................25 4.2 FRAMER LOOPBACK .....................................................................................................................28 4.3 AUTOMATIC ALARM GENERATION ...............................................................................................29 4.4 REMOTE LOOPBACK .....................................................................................................................30 4.5 LOCAL LOOPBACK........................................................................................................................30 STATUS AND INFORMATION REGISTERS .............................................................................32 5.1 CRC4 SYNC COUNTER .................................................................................................................34 ERROR COUNT REGISTERS........................................................................................................39 6.1 BPV OR CODE VIOLATION COUNTER ...........................................................................................39 6.2 CRC4 ERROR COUNTER ...............................................................................................................40 6.3 E-BIT/PRBS BIT ERROR COUNTER ..............................................................................................40 6.4 FAS ERROR COUNTER..................................................................................................................41 DS0 MONITORING FUNCTION ...................................................................................................42 PRBS GENERATION AND DETECTION ....................................................................................45 SYSTEM CLOCK INTERFACE.....................................................................................................46
4.
5. 6.
7. 8. 9.
10. TRANSMIT CLOCK SOURCE ......................................................................................................47 11. IDLE CODE INSERTION................................................................................................................48 12. PER-CHANNEL LOOPBACK ........................................................................................................49 13. ELASTIC STORE OPERATION ....................................................................................................49 14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .....................................50 15. USER-CONFIGURABLE OUTPUTS.............................................................................................53 16. LINE INTERFACE UNIT ................................................................................................................56 16.1 RECEIVE CLOCK AND DATA RECOVERY .......................................................................................56 16.2 TERMINATION...............................................................................................................................57 16.3 RECEIVE MONITOR MODE ............................................................................................................57 16.4 TRANSMIT WAVESHAPING AND LINE DRIVING .............................................................................59 16.5 JITTER ATTENUATORS ..................................................................................................................62
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17. CMI (CODE MARK INVERSION).................................................................................................64 18. INTERLEAVED PCM BUS OPERATION....................................................................................66 19. FUNCTIONAL TIMING DIAGRAMS...........................................................................................68 19.1 RECEIVE TIMING DIAGRAMS ........................................................................................................68 19.2 TRANSMIT TIMING DIAGRAMS......................................................................................................70 20. OPERATING PARAMETERS ........................................................................................................74 21. AC TIMING PARAMETERS AND DIAGRAMS .........................................................................75 21.1 MULTIPLEXED BUS AC CHARACTERISTICS ..................................................................................75 21.2 NONMULTIPLEXED BUS AC CHARACTERISTICS ...........................................................................78 21.3 SERIAL PORT ................................................................................................................................81 21.4 RECEIVE AC CHARACTERISTICS...................................................................................................82 21.5 TRANSMIT AC CHARACTERISTICS ................................................................................................84 21.6 SPECIAL MODES AC CHARACTERISTICS.......................................................................................86 22. PACKAGE INFORMATION...........................................................................................................87
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DS21Q50
LIST OF FIGURES
Figure 1-1. Block Diagram ............................................................................................................................8 Figure 3-1. Serial Port Operation Mode 1 ...................................................................................................21 Figure 3-2. Serial Port Operation Mode 2 ...................................................................................................21 Figure 3-3. Serial Port Operation Mode 3 ...................................................................................................22 Figure 3-4. Serial Port Operation Mode 4 ...................................................................................................22 Figure 16-1. Typical Monitor Port Application...........................................................................................57 Figure 16-2. External Analog Connections (Basic Configuration) .............................................................60 Figure 16-3. External Analog Connections (Protected Interface) ...............................................................60 Figure 16-4. Transmit Waveform Template................................................................................................61 Figure 16-5. Jitter Tolerance........................................................................................................................63 Figure 16-6. Jitter Attenuation.....................................................................................................................63 Figure 17-1. CMI Coding ............................................................................................................................64 Figure 17-2. CMI Code Violation Example ................................................................................................65 Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) ............................67 Figure 19-1. Receive Frame and Multiframe Timing..................................................................................68 Figure 19-2. Receive Boundary Timing (With Elastic Store Disabled)......................................................68 Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) .......................................................69 Figure 19-4. Receive Interleave Bus Operation ..........................................................................................69 Figure 19-5. Transmit Frame and Multiframe Timing ................................................................................70 Figure 19-6. Transmit Boundary Timing.....................................................................................................70 Figure 19-7. Transmit Interleave Bus Operation.........................................................................................71 Figure 19-8. Framer Synchronization Flowchart.........................................................................................72 Figure 19-9. Transmit Data Flow ................................................................................................................73 Figure 21-1. Intel Bus Read AC Timing (PBTS = 0) ..................................................................................76 Figure 21-2. Intel Bus Write Timing (PBTS = 0)........................................................................................76 Figure 21-3. Motorola Bus AC Timing (PBTS = 1)....................................................................................77 Figure 21-4. Intel Bus Read Timing (PBTS = 0).........................................................................................79 Figure 21-5. Intel Bus Write Timing (PBTS = 0)........................................................................................79 Figure 21-6. Motorola Bus Read Timing (PBTS = 1) .................................................................................80 Figure 21-7. Motorola Bus Write Timing (PBTS = 1) ................................................................................80 Figure 21-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0) ..............................................................................81 Figure 21-9. Receive AC Timing (Receive Elastic Store Disabled) ...........................................................82 Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled) ..........................................................83 Figure 21-11. Transmit AC Timing (IBO Disabled) ...................................................................................85 Figure 21-12. Transmit AC Timing (IBO Enabled) ....................................................................................85 Figure 21-13. NRZ Input AC Timing..........................................................................................................86
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LIST OF TABLES
Table 2-1. Pin Assignments (by Function) ....................................................................................................9 Table 2-2. Pin Assignment (by LQFP Pin Number)....................................................................................12 Table 3-1. Bus Mode Select.........................................................................................................................20 Table 3-2. Register Map ..............................................................................................................................23 Table 4-1. Sync/Resync Criteria..................................................................................................................26 Table 5-1. Alarm Criteria ............................................................................................................................34 Table 8-1. Transmit PRBS Mode Select......................................................................................................45 Table 8-2. Receive PRBS Mode Select .......................................................................................................45 Table 9-1. Master Port Selection .................................................................................................................47 Table 9-2. Synthesizer Output Select ..........................................................................................................47 Table 15-1. OUTA and OUTB Function Select ..........................................................................................55 Table 16-1. Receive Monitor Mode Gain....................................................................................................57 Table 16-2. Monitor Mode Settings.............................................................................................................58 Table 16-3. Line Build-Out Select in LICR ................................................................................................59 Table 16-4. Transformer Specifications ......................................................................................................59 Table 18-1. IBO Device Assignment...........................................................................................................66 Table 18-2. IBO System Clock Select.........................................................................................................67
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1. INTRODUCTION
The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included for this type of application: the interleave bus option (IBO) and a system clock synthesizer feature. The IBO allows up to eight E1 data streams to be multiplexed onto a single high-speed PCM bus without additional external logic. The system clock synthesizer feature allows any of the E1 lines to be selected as the master source of clock for the system and for all the transmitters. This is also accomplished without the need of external logic. Each of the four transceivers has a clock and data jitter attenuator that can be assigned to either the transmit or receive path. In addition there is a single, undedicated clock jitter attenuator that can be hardware configured as the user needs. Each transceiver also contains a PRBS pattern generator and detector. Figure 18-1 shows a simplified typical application that terminates eight E1 lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The 16.384MHz system clock is derived and phased-locked to one of the eight E1 lines. On the receive side of each port, an elastic store provides logical management of any slip conditions because of the asynchronous relationship of the eight E1 lines. In this application, all eight transmitters are timed to the selected E1 line. The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS21Q50. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive framer where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS21Q50 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of 0dB to -43dB, which allows the device to operate on cables over 2km in length. The receive framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the receive elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input. The clock applied at the SYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The transmit framer is independent from the receive in both the clock requirements and characteristics. The transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
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Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125s frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1; time slot 1 is identical to channel 2; and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8. Bit number 1, MSB, is transmitted first. Bit number 8, the LSB, is transmitted last. The term "locked" is used to refer to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., a 8.192MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations are used:
NAME FAS CAS MF Si CRC4 CCS Sa E-Bit LOC TCLK RCLK FUNCTION Frame Alignment Signal Channel Associated Signaling Multiframe International bits Cyclical Redundancy Check Common Channel Signaling Additional bits CRC4 Error Bits Loss of Clock This generally refers to the transmit rate clock and can reference an actual input signal to the device (TCLK) or an internally derived signal used for transmission. This generally refers to the recovered network clock and can be a reference to an actual output signal from the device or an internal signal.
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Figure 1-1. Block Diagram
MCL
VCO/PLL User Outputs Select
OUTA OUTB RSER1 SYSCLK1 RSYNC1
RECEIVE SIDE
RRING1 RTIP1
DATA CLOCK SYNC Remote Loopback Receive-Side Framer
Elastic Store And IBO Buffer
TRANSMIT SIDE
Transmit Line I/F
Receive Line I/F Clock / Data Recovery Local Loopback
Jitter Attenuator Either transmit or receive path
Framer Loopback
Sync Control DATA CLOCK SYNC Transmit-Side Formatter A BU Ck B MUX C IBO Buffer Divide by 2/4/8 Tx Ck MUX LOTC Detect A B
TRING1 TTIP1
TSYNC1 TSER1
TCLK1
TRANSCEIVER 1of 4
TRANSMIT CLOCK SOURCE
Backup Clock MUX Transceivers 2, 3, and 4 RCLK Transceiver 2 RCLK Transceiver 3 RCLK Transceiver 4 MUX
SYSTEM INTERFACE
2.048MHz
Parallel & Test Control Port (routed to all blocks)
Alternate Jitter Attenuator 4/8/16MHz Synthesizer
REFCLK 4/8/16MCK
INT D0 to D7/ AD0 to AD7 A0 to A4 ALE(AS)/A5 RD(DS) WR(R/W) TS0 TS1 BTS BTS PBT CS
AJACKI
AJACOI
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2. PIN DESCRIPTION Table 2-1. Pin Assignments (by Function)
NAME PIN 71 45 46 47 48 49 70 69 50 96 97 98 19 20 21 22 23 24 25 44 84 59 34 9 83 58 33 8 -- -- -- -- 94 73 61 36 11 86 PARALLEL PORT ENABLED 4/8/16MCK A0 A1 A2 A3 A4 AJACKI AJACKO ALE(AS)/A5 BTS0 BTS1 CS D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 DVDD1 DVDD2 DVDD3 DVDD4 DVSS1 DVSS2 DVSS3 DVSS4 EQVSS1 EQVSS2 EQVSS3 EQVSS4 INT MCLK OUTA1 OUTA2 OUTA3 OUTA4
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SERIAL PORT ENABLED
TYPE O
FUNCTION [Serial Port Mode in Brackets] 4.096MHz, 8.192MHz, or 16.384 MHz Clock Address Bus Bit 0/Serial Port [Input Clock Edge Select] Address Bus Bit 1/Serial Port [Output Clock Edge Select] Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Alternate Jitter Attenuator Clock Input Alternate Jitter Attenuator Clock Output Address Latch Enable/Address Bus Bit 5 Bus Type Select 0 Bus Type Select 1 Chip Select Data Bus Bit0/Address/Data Bus Bit 0 Data Bus Bit1/Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus Bit2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 [Serial Data Output] Digital Positive Supply Digital Positive Supply Digital Positive Supply Digital Positive Supply Digital Signal Ground Digital Signal Ground Digital Signal Ground Digital Signal Ground Equalizer Analog Signal Ground Equalizer Analog Signal Ground Equalizer Analog Signal Ground Equalizer Analog Signal Ground Interrupt Master Clock Input User Selectable Output A User Selectable Output A User Selectable Output A User Selectable Output A
ICES OCES
I I I I I I O I
I I/O I/O I/O I/O I/O I/O I/O SDO I/O -- -- -- -- -- -- -- -- -- -- -- -- O I O O O O
DS21Q50
NAME PIN 60 35 10 85 95 75 72 67 42 17 92 63 38 13 88 64 39 14 89 66 41 16 91 93 68 43 18 90 65 40 15 62 37 12 87 80 55 30 5 79 54 29 4 99 100 81 PARALLEL PORT ENABLED OUTB1 OUTB2 OUTB3 OUTB4 PBTS RD (DS) REFCLK RRING1 RRING2 RRING3 RRING4 RSER1 RSER2 RSER3 RSER4 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RTIP1 RTIP2 RTIP3 RTIP4 RVDD1 RVDD2 RVDD3 RVDD4 RVSS1 RVSS2 RVSS3 RVSS4 SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 TCLK1 TCLK2 TCLK3 TCLK4 TRING1 TRING2 TRING3 TRING4 TS0 TS1 TSER1 SERIAL PORT ENABLED TYPE O O O O I I I/O I I I I O O O O I/O I/O I/O I/O I I I I -- -- -- -- -- -- -- -- I I I I I I I I O O O O I I I
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FUNCTION [Serial Port Mode in Brackets] User Selectable Output B User Selectable Output B User Selectable Output B User Selectable Output B Parallel Bus Type Select Read Input (Data Strobe)[Serial Port Clock] Reference Clock Receive Analog Ring Input Receive Analog Ring Input Receive Analog Ring Input Receive Analog Ring Input Receive Serial Data Receive Serial Data Receive Serial Data Receive Serial Data Receive Sync Receive Sync Receive Sync Receive Sync Receive Analog Tip Input Receive Analog Tip Input Receive Analog Tip Input Receive Analog Tip Input Receive Analog Positive Supply Receive Analog Positive Supply Receive Analog Positive Supply Receive Analog Positive Supply Receive Analog Signal Ground Receive Analog Signal Ground Receive Analog Signal Ground Receive Analog Signal Ground Transmit/Receive System Clock Transmit/Receive System Clock Transmit/Receive System Clock Transmit/Receive System Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Analog Ring Output Transmit Analog Ring Output Transmit Analog Ring Output Transmit Analog Ring Output Transceiver Select 0 Transceiver Select 1 Transmit Serial Data
SCLK
DS21Q50
NAME PIN 56 31 6 82 57 32 7 76 51 26 1 78 53 28 3 77 52 27 2 74 PARALLEL PORT ENABLED TSER2 TSER3 TSER4 TSYNC1 TSYNC2 TSYNC3 TSYNC4 TTIP1 TTIP2 TTIP3 TTIP4 TVDD1 TVDD2 TVDD3 TVDD4 TVSS1 TVSS2 TVSS3 TVSS4 WR (R/W) SERIAL PORT ENABLED TYPE I I I I/O I/O I/O I/O O O O O -- -- -- -- -- -- -- -- I
FUNCTION [Serial Port Mode in Brackets] Transmit Serial Data Transmit Serial Data Transmit Serial Data Transmit Sync Transmit Sync Transmit Sync Transmit Sync Transmit Analog Tip Output Transmit Analog Tip Output Transmit Analog Tip Output Transmit Analog Tip Output Transmit Analog Positive Supply Transmit Analog Positive Supply Transmit Analog Positive Supply Transmit Analog Positive Supply Transmit Analog Signal Ground Transmit Analog Signal Ground Transmit Analog Signal Ground Transmit Analog Signal Ground Write Input (Read/Write) [Serial Data Input]
SDI
Note: EQVSS lines are tied to RVSS lines in the 100-pin LQFP package.
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Table 2-2. Pin Assignment (by LQFP Pin Number)
NAME PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PARALLEL PORT ENABLED TTIP4 TVSS4 TVDD4 TRING4 TCLK4 TSER4 TSYNC4 DVSS4 DVDD4 OUTB3 OUTA3 SYSCLK3 RSER3 RSYNC3 RVSS4 RTIP3 RRING3 RVDD4 D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 TTIP3 TVSS3 TVDD3 TRING3 TCLK3 TSER3 TSYNC3 DVSS3 DVDD3 OUTB2 OUTA2 SYSCLK2 RSER2 RSYNC2 RVSS3 RTIP2 RRING2 RVDD3 D7/AD7 SERIAL PORT ENABLED TYPE O -- -- O I I I/O -- -- O O I O I/O -- I I -- I/O I/O I/O I/O I/O I/O I/O O -- -- O I I I/O -- -- O O I O I/O -- I I -- I/O
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FUNCTION [Serial Port Mode in Brackets] Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Data Bus Bit0/Address/Data Bus Bit 0 Data Bus Bit1/ Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus Bit2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Data Bus Bit 7/Address/Data Bus Bit 7
SDO
DS21Q50
NAME PIN PARALLEL PORT ENABLED A0 A1 A2 A3 A4 ALE (AS)/A5 TTIP2 TVSS2 TVDD2 TRING2 TCLK2 TSER2 TSYNC2 DVSS2 DVDD2 OUTB1 OUTA1 SYSCLK1 RSER1 RSYNC1 RVSS2 RTIP1 RRING1 RVDD2 AJACKO AJACKI 4/8/16MCK REFCLK MCLK WR (R/W) RD (DS) TTIP1 TVSS1 TVDD1 TRING1 TCLK1 TSER1 TSYNC1 DVSS1 DVDD1 OUTB4 OUTA4 SERIAL PORT ENABLED ICES OCES TYPE FUNCTION [Serial Port Mode in Brackets] [Serial Data Output] Address Bus Bit 0/Serial Port [Input Clock Edge Select] Address Bus Bit 1/Serial Port [Output Clock Edge Select] Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Latch Enable/Address Bus Bit 5 Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Alternate Jitter Attenuator Clock Output Alternate Jitter Attenuator Clock Input 4.096MHz, 8.192MHz, or 16.384MHz Clock Reference Clock Master Clock Input Write Input (Read/Write) [Serial Data Input] Read Input (Data Strobe) [Serial Port Clock] Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
I I I I I I O -- -- O I I I/O -- -- O O I O I/O -- I I -- O I O I/O I I I O -- -- O I I I/O -- -- O O
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SDI SCLK
DS21Q50
NAME PIN 87 88 89 90 91 92 93 94 95 96 97 98 99 100 -- -- -- -- PARALLEL PORT ENABLED SYSCLK4 RSER4 RSYNC4 RVSS1 RTIP4 RRING4 RVDD1 INT PBTS BTS0 BTS1 CS TS0 TS1 EQVSS1 EQVSS2 EQVSS3 EQVSS4 SERIAL PORT ENABLED TYPE I O I/O - I I -- O I FUNCTION [Serial Port Mode in Brackets] Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Interrupt Parallel Bus Type Select Bus Type Select 0 Bus Type Select 1 Chip Select Transceiver Select 0 Transceiver Select 1 Equalizer Analog Signal Ground Equalizer Analog Signal Ground Equalizer Analog Signal Ground Equalizer Analog Signal Ground
I I I -- -- -- --
Note: EQVSS lines are tied to RVSS lines in the 100-pin LQFP package.
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2.1 Pin Function Description
2.1.1 System (Backplane) Interface Pins
Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when IBO disabled. Sampled on the falling edge of SYSCLK when the IBO function is enabled. Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output As an input, pulse at this pin establishes either frame or multiframe boundaries for the transmitter. As an output, can be programmed to output either a frame or multiframe pulse. Signal Name: RSER Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive elastic store is disabled. Updated on the rising edges of SYSCLK when the receive elastic store is enabled. Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin, which identifies either frame or CAS/CRC4 multiframe boundaries. If the receive elastic store is enabled, then this pin can be enabled to be an input at which a frame boundary pulse synchronous with SYSCLK is applied. Signal Name: SYSCLK Signal Description: System Clock Signal Type: Input 2.048MHz clock that is used to clock data out of the receive elastic store. When the IBO is enabled this can be a 4.096MHz, 8.192MHz, or 16.384MHz clock. Signal Name: OUTA Signal Description: User Selectable Output A Signal Type: Output A multifunction pin that can be programmed by the host to output various alarms, clocks or data, or used to control external circuitry. Signal Name: OUTB Signal Description: User Selectable Output B Signal Type: Output A multifunction pin that can be programmed by the host to output various alarms, clocks, or data, or used to control external circuitry.
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2.1.2 Alternate Jitter Attenuator
Signal Name: AJACKI Signal Description: Alternate Jitter Attenuator Clock Input Signal Type: Input Clock input to alternate jitter attenuator. Signal Name: AJACKO Signal Description: Alternate Jitter Attenuator Clock Output Signal Type: Output Clock output of alternate jitter attenuator.
2.1.3 Clock Synthesizer
Signal Name: 4/8/16MCK Signal Description: 4.096MHz/8.192MHz/16.384MHz Clock Output Signal Type: Output A 4.096MHz, 8.192MHz, or 16.384MHz clock output that is referenced to one of the four recovered line clocks (RCLKs) or to an external 2.048MHz reference. Signal Name: REFCLK Signal Description: Reference Clock Signal Type: Input/Output Can be configured as an output to source a 2.048MHz reference clock or as an input to supply a 2.048MHz reference clock from an external source to the clock synthesizer.
2.1.4 Parallel Port Control Pins
Signal Name: INT Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and change of conditions defined in status registers 1 and 2 and the HDLC status register. Active-low, open-drain output. Signal Name: BTS0 Signal Description: Bus Type Select Bit 0 Signal Type: Input Used with BTS1 to select between muxed, nonmuxed, serial bus operation, and output high-Z mode. Signal Name: BTS1 Signal Description: Bus Type Select Bit 0 Signal Type: Input Used with BTS0 to select between muxed, nonmuxed, serial bus operation, and output high-Z mode. Signal Name: TS0 Signal Description: Transceiver Select Bit 0 Signal Type: Input Used with TS1 to select one of four transceivers. Signal Name: TS1 Signal Description: Transceiver Select Bit 0 Signal Type: Input Used with TS0 to select one of four transceivers.
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Signal Name: PBTS Signal Description: Parallel Bus Type Select Signal Type: Input Used to select between Motorola and Intel parallel bus types. Signal Name: Signal Description: AD0 to AD7/SDO Data Bus or Address/Data Bus [D0 to D6] Data Bus or Address/Data Bus [D7]/Serial Port Output Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed address/data bus. Signal Name: A0 to A4 Signal Description: Address Bus Signal Type: Input In nonmultiplexed bus operation, this serves as the address bus. In multiplexed bus operation, these pins are not used and should be wired low. Signal Name: RD(DS)/SCLK Signal Description: Read Input--Data Strobe/Serial Port Clock Signal Type: Input RD and DS are active-low signals. DS active HIGH when in multiplexed mode. See bus-timing diagrams. Signal Name: CS Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS is an active low signal. Signal Name: ALE (AS)/A5 Signal Description: Address Latch Enable (Address Strobe) or A6 Signal Type: Input In nonmultiplexed bus operation, this serves as the upper address bit. In multiplexed bus operation, this serves to demultiplex the bus on a positive-going edge. Signal Name: WR (R/W)/SDI Signal Description: Write Input (Read/Write)/Serial Port Data Input Signal Type: Input WR is an active-low signal.
2.1.5 Serial Port Control Pins
Signal Name: SDO Signal Description: Serial Port Output Signal Type: Output Data at this output can be updated on the rising or falling edge of SCLK. Signal Name: SDI Signal Description: Serial Port Data Input Signal Type: Input Data at this input can be sampled on the rising or falling edge of SCLK.
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Signal Name: ICES Signal Description: Input Clock Edge Select Signal Type: Input Used to select which SCLK clock edge samples data at SDI. Signal Name: OCES Signal Description: Output Clock Edge Select Signal Type: Input Used to select which SCLK clock edge updates data at SDO. Signal Name: SCLK Signal Description: Serial Port Clock Signal Type: Input Used to clock data into and out of the serial port.
2.1.6 Line Interface Pins
Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048MHz (50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. Signal Name: RTIP and RRING Signal Description: Receive Tip and Ring Signal Type: Input Analog inputs for clock recovery circuitry. These pins connect through a 1:1 transformer to the E1 line. See Section 16 for details. Signal Name: TTIP and TRING Signal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect through a 1:2 step-up transformer to the E1 line. See Section 16 for details.
2.1.7 Supply Pins
Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V 5%. Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V 5%. Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 3.3V 5%. Should be tied to the RVDD and DVDD pins.
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Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply 0V. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and TVSS. Signal Name: EQVSS Signal Description: Receiver Equalizer Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and TVSS. Not accessible in the 100-pin LQFP package. Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and RVSS.
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3. HOST INTERFACE PORT
The DS21Q50 is controlled either through a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Table 3-1 for a description of the bus configurations. All Motorola bus signals are listed in parentheses (). See Functional Timing Diagrams in Section 19 for more details.
Table 3-1. Bus Mode Select
PBTS 0 0 1 1 X X BTS1 0 0 0 0 1 1 BTS0 0 1 0 1 0 1 PARALLEL PORT MODE Intel Multiplexed Intel Nonmultiplexed Motorola Multiplexed Motorola Nonmultiplexed Serial TEST (Outputs High-Z)
3.1 Parallel Port Operation
When using the parallel interface on the DS21Q50 (BTS1 = 0) the user has the option for either multiplexed bus operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q50 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in AC Timing Parameters and Diagrams in Section 21 for more details.
3.2 Serial Port Operation
Setting BTS1 pin = 1 and the BTS0 pin = 0 enables the serial bus interface on the DS21Q50. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 21 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 for more details. Reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write (0). The next five bits identify the register address. The next bit is reserved and must be set to 0 for proper operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The burst mode causes all registers to be consecutively written or read. All data transfers are initiated by driving the CS input low. When input clock-edge select (ICES) is low, input data is latched on the rising edge of SCLK. When ICES is high, input data is latched on the falling edge of SCLK. When output clock-edge select (OCES) is low, data is output on the falling edge of SCLK. When OCES is high, data is output on the rising edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is three-stated when CS is high.
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Figure 3-1. Serial Port Operation Mode 1
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SDI R/W (lsb) SDO A0 A1 A2 A3 A4 A5 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
Figure 3-2. Serial Port Operation Mode 2
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SDI R/W (lsb) SDO A0 A1 A2 A3 A4 A5 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
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Figure 3-3. Serial Port Operation Mode 3
ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SDI R/W (lsb) SDO A0 A1 A2 A3 A4 A5 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
Figure 3-4. Serial Port Operation Mode 4
ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SDI R/W (lsb) SDO A0 A1 A2 A3 A4 A5 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
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3.3 Register Map Table 3-2. Register Map
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B R/W R R R R R R R R R/W R R/W R/W -- -- -- R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R R R/W NAME VCR1 VCR2 CRCCR1 CRCCR2 EBCR1 EBCR2 FASCR1 FASCR2 RIR SSR SR1 SR2 -- -- -- IDR RCR TCR CCR1 CCR2 CCR3 CCR4 CCR5 LICR IMR1 IMR2 OUTAC OUTBC IBO SCICR TEST2 (set to 00h) RMM TAF TNAF TDS0M TIDR TIR1 TIR2 TIR3 TIR4 RAF RNAF RDS0M PCLB1 FUNCTION BPV or Code Violation Count 1 BPV or Code Violation Count 2 CRC4 Error Count 1 CRC4 Error Count 2 E-Bit Count 1/PRBS Error Count 1 E-Bit Count 2/PRBS Error Count 2 FAS Error Count 1 FAS Error Count 2 Receive Information Synchronizer Status Status 1 Status 2 Unused Unused Unused Device ID (Note 1) Receive Control Transmit Control 1 Common Control 1 Common Control 2 Common Control 3 Common Control 4 Common Control 5 Line Interface Control Register Interrupt Mask 1 Interrupt Mask 2 Output A Control Output B Control Interleave Bus Operation Register System Clock Interface Control Register (Note 1) Test 2 (Note 2) Receive Monitor Mode Transmit Align Frame Transmit Nonalign Frame Transmit DS0 Monitor Transmit Idle Definition Transmit Idle 1 Transmit Idle 2 Transmit Idle 3 Transmit Idle 4 Receive Align Frame Receive Nonalign Frame Receive DS0 Monitor Per-Channel Loopback Control 1
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ADDRESS 2C 2D 2E 2F
Note 1: Note 2:
R/W R/W R/W R/W R/W
NAME PCLB2 PCLB3 PCLB4 TEST1 (set to 00h)
FUNCTION Per-Channel Loopback Control 2 Per-Channel Loopback Control 3 Per-Channel Loopback Control 4 Test 1 (Note 2)
The device ID register and the system clock interface control register exist in Transceiver 1 only. (TS0, TS1 = 0). Only the factory uses the test registers; these registers must be cleared (set to all zeros) on power-up initialization to ensure proper operation.
4. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21Q50 is configured through a set of seven control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers only need to be accessed when there is a change in the system configuration. There is one receive control register (RCR), one transmit control register (TCR), and five common control registers (CCR1 to CCR5). Each of these registers is described in this section. There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed to 1, indicating that an E1 quad transceiver is present. The next three MSBs are reserved for future use. The lower 4 bits of the device ID register are used to identify the revision of the device. This register exists in Transceiver 1 only (TS0, TS1 = 0). The test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On power-up, the test registers should be set to 00h in order for the DS21Q50 to operate properly.
Register Name: Register Description: Register Address: Bit Name BIT 7 6 5 4 3 1 2 0 7 1 NAME 1 0 0 0 ID3 ID2 ID1 ID0 IDR Device Identification Register 0F Hex 6 0 5 0 4 0 3 ID3 2 ID2 1 ID1 0 ID0
FUNCTION Bit 7 Bit 6 Bit 5 Bit 4 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2 Chip Revision Bit 1 Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
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4.1 Power-Up Sequence
On power-up and after the supplies are stable, the DS21Q50 should be configured for operation by writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry (it takes the device about 40ms to recover from the LIRST bit being toggled). Finally, after the SYSCLK input is stable, the ESR bits (CCR4.5 and CCR4.6) should be toggled from a 0 to 1 (this step can be skipped if the elastic store is disabled).
Register Name: Register Description: Register Address: Bit Name NAME RSMF 7 RSMF BIT 7 RCR Receive Control Register 10 Hex 6 RSM 5 RSIO 4 RESE 3 -- 2 FRC 1 SYNC 0 RESYNC
FUNCTION RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR.6 = 1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries RSYNC Mode Select. 0 = frame mode (See the timing diagrams in Section 19.1.) 1 = multiframe mode (See the timing diagrams in Section 19.1.) RSYNC I/O Select. (Note: This bit must be set to 0 when RCR .4 = 0). 0 = RSYNC is an output (depends on RCR.6) 1 = RSYNC is an input (only valid if elastic store enabled) Receive Elastic Store Enable 0 = elastic store is bypassed 1 = elastic store is enabled Unused. Should be set = 0 for proper operation Frame Resync Criteria 0 = resync if FAS received in error three consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times Sync Enable 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.
RSM RSIO RESE -- FRC SYNCE RESYNC
6 5 4 3 2 1 0
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Table 4-1. Sync/Resync Criteria
FRAME OR MULTIFRAME LEVEL FAS CRC4 CAS SYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 Two valid MF alignment words found within 8ms Valid MF alignment word found and previous time slot 16 contains code other than all zeros RESYNC CRITERIA Three consecutive incorrect FAS received; Alternate (RCR1.2 = 1) the above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 codewords out of 1000 received in error Two consecutive MF alignment words received in error ITU SPEC. G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5.2
Register Name: Register Description: Register Address: Bit Name NAME 7 IFSS BIT
TCR Transmit Control Register 11 Hex 6 TFPT 5 AEBE 4 TUA1 3 TSiS 2 TSA1 1 TSM 0 TSIO
FUNCTION Internal Frame Sync Select 0 = TSYNC normal 1 = If TSYNC is in the INPUT mode (TSIO = 0) then TSYNC is internally replaced by the recovered receive frame sync. The TSYNC pin is ignored. 1 = If TSYNC is in the OUTPUT mode (TSIO = 1), TSYNC outputs the recovered multiframe frame sync. Transmit Time Slot 0 Pass-Through 0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/remote alarm sourced from TSER Automatic E-Bit Enable 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Transmit Unframed All Ones 0 = transmit data normally 1 = transmit an unframed all-ones code Transmit International Bit Select 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR.6 must be set to 0) Transmit Signaling All Ones 0 = normal operation 1 = force time slot 16 in every frame to all ones TSYNC Mode Select 0 = frame mode (See the timing diagrams in Section 19.2.) 1 = CAS and CRC4 multiframe mode (See the timing diagrams in Section 19.2.) TSYNC I/O Select 0 = TSYNC is an input 1 = TSYNC is an output
IFSS
7
TFPT AEBE TUA1 TSiS TSA1 TSM TSIO
6 5 4 3 2 1 0
Note: See Figure 19-9 for more details about how the transmit control register affects the operation of the DS21Q50.
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Register Name: Register Description: Register Address: Bit Name NAME FLB THDB3 TIBE TCRC4 7 FLB BIT 7 6 5 4
CCR1 Common Control Register 1 12 Hex 5 TIBE 4 TCRC4 3 RSMS 2 RHDB3 1 PCLMS 0 RCRC4
6 THDB3
FUNCTION Framer Loopback. See Section 4.2 for details. 0 = loopback disabled 1 = loopback enabled Transmit HDB3 Enable 0 = HDB3 disabled 1 = HDB3 enabled Transmit Insert Bit Error. A 0-to-1 transition causes a single bit error to be inserted in the transmit path. Transmit CRC4 Enable 0 = CRC4 disabled 1 = CRC4 enabled Receive Signaling Mode Select 0 = CAS signaling mode. Receiver searches for the CAS MF alignment signal. 1 = CCS signaling mode. Receiver does not search for the CAS MF alignment signal. Receive HDB3 Enable 0 = HDB3 disabled 1 = HDB3 enabled Per Channel Loopback Mode Select. See Section 12 for details 0 = remote per channel loopback 1 = local per channel loopback Receive CRC4 Enable 0 = CRC4 disabled 1 = CRC4 enabled
RSMS
3
RHDB3
2
PCLMS
1
RCRC4
0
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4.2 Framer Loopback
When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode (Figure 1-1). This loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter back to the receiver. When FLB is enabled, the following occurs: 1) Data is transmitted as normal at TTIP and TRING. 2) The RCLK output is replaced with the TCLK input.
Register Name: Register Description: Register Address: Bit Name 7 RCUS BIT 7 6 5 4 3 CCR2 Common Control Register 2 13 Hex 6 VCRFS 5 AAIS 4 ARA 3 RSERC 2 LOTCMC 1 RCLA 0 TCSS
SYMBOL ECUS VCRFS AAIS ARA RSERC
LOTCMC
2
RCLA
1
TCSS
0
FUNCTION Error Counter Update Select. See Section 6 for details. 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) VCR Function Select. See Section 6 for details. 0 = count bipolar violations (BPVs) 1 = count code violations (CVs) Automatic AIS Generation 0 = disabled 1 = enabled Automatic Remote Alarm Generation 0 = disabled 1 = enabled RSER Control 0 = allow RSER to output data as received under all conditions 1 = force RSER to one under loss-of-frame alignment conditions Loss-of-Transmit Clock Mux Control. Determines whether the transmit formatter should switch to the ever present RCLK if the TCLK should fail to transition (Figure 1-1). 0 = do not switch to RCLK if TCLK stops 1 = switch to RCLK if TCLK stops Receive Carrier Loss (RCL) Alternate Criteria 0 = RCL declared upon 255 consecutive 0s (125ms) 1 = RCL declared upon 2048 consecutive 0s (1ms) Transmit Clock Source Select. This function allows the user to internally select RCLK as the clock source for the transmit formatter. 0 = source of transmit clock determined by CCR2.2 (LOTCMC) 1 = force transmitter to internally switch to RCLK as source of transmit clock. Signal at TCLK pin is ignored
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4.3 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer forces an AIS alarm. When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal), or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted if the DS21Q50 cannot find CRC4 multiframe synchronization within 400ms as per G.706.
Register Name: Register Description: Register Address: Bit Name NAME RLB LLB LIAIS TCM4 TCM3 TCM2 TCM1 TCM0 7 RLB BIT 7 6 5 4 3 2 1 0 CCR3 Common Control Register 14 Hex 6 LLB 5 LIAIS 4 TCM4 3 TCM3 2 TCM2 1 TCM1 0 TCM0
FUNCTION Remote Loopback. See Section 4.4 for details. 0 = loopback disabled 1 = loopback enabled Local Loopback. See Section 4.5 for details. 0 = loopback disabled 1 = loopback enabled Line Interface AIS Generation Enable 0 = allow normal data to be transmitted at TTIP and TRING 1 = force unframed all ones to be transmitted at TTIP and TRING at the MCLK rate Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data appear in the TDS0M register. See Section 6 or details. Transmit Channel Monitor Bit 3 Transmit Channel Monitor Bit 2 Transmit Channel Monitor Bit 1 Transmit Channel Monitor Bit 0. LSB of the channel decode.
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4.4 Remote Loopback
When CCR4.7 is set to 1, the DS21Q50 is forced into remote loopback (RLB). In this loopback, data input through the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues to pass through the receive framer of the DS21Q50 as it would normally and the data from the transmit formatter is ignored (Figure 1-1).
4.5 Local Loopback
When CCR4.6 is set to 1, the DS21Q50 is forced into local loopback (LLB). In this loopback, data continues to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data being transmitted. Data in this loopback passes through the jitter attenuator (Figure 1-1).
Register Name: Register Description: Register Address: Bit Name 7 LIRST BIT 7 CCR4 Common Control Register 4 15 Hex 6 RESA 5 RESR 4 RCM4 3 RCM3 2 RCM2 1 RCM1 0 RCM0
NAME LIRST
FUNCTION Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Receive Elastic Store Align. Setting this bit from a 0 to 1 can force the receive elastic store's write/read pointers to a minim separation of half a frame. No action is taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed and data is disrupted. Should be toggled after SYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details. Receive Elastic Store Reset. Setting this bit from a 0 to 1 forces the receive elastic store to a depth of one frame. Receive data is lost during the reset. Should be toggled after SYSCLK has been applied and is stable. Must be cleared and set again for a subsequent reset. See Section 13 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data appears in the RDS0M register. See Section 6 for details. Receive Channel Monitor Bit 3 Receive Channel Monitor Bit 2 Receive Channel Monitor Bit 1 Receive Channel Monitor Bit 0. LSB of the channel decode.
RESA
6
RESR RCM4 RCM3 RCM2 RCM1 RCM0
5 4 3 2 1 0
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Register Name: Register Description: Register Address: Bit Name 7 LIUODO BIT
CCR5 Common Control Register 5 16 Hex 6 CDIG 5 LIUSI 4 IRTSEL 3 TPRBS1 2 TPRBS0 1 RPRBS1 0 RPRBS0
NAME
FUNCTION Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs are open drain or not. The line driver outputs can be forced open drain to allow 6V peak pulses to be generated or to allow the creation of a very low-power interface. 0 = allow TTIP and TRING to operate normally 1 = force the TTIP and TRING outputs to be open drain Customer Disconnect Indication Generator. This control bit determines whether the line interface generates an unframed ...1010... pattern at TTIP and TRING instead of the normal data pattern. 0 = generate normal data at TTIP and TRING 1 = generate a ...1010... pattern at TTIP and TRING Line Interface G.703 Synchronization Interface Enable. This control bit determines whether the line receiver should handle a normal E1 signal (Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10 of G.703). This control has no affect on the line interface transmitter. 0 = line receiver configured to support a normal E1 signal 1 = line receiver configured to support a synchronization signal Receive Termination Select. This function applies internal parallel resistance to the normal 120W external termination to create a 75W termination. 0 = normal 120W external termination 1 = internally adjust receive termination to 75W Transmit PRBS Mode Bit 1 (Table 8-1) Transmit PRBS Mode Bit 0 (Table 8-1) Receive PRBS Mode Bit 1 (Table 8-2) Receive PRBS Mode Bit 0 (Table 8-2)
LIUODO
7
CDIG
6
LIUSI
5
IRTSEL TPRBS1 TPRBS0 RPRBS1 RPRBS0
4 3 2 1 0
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5. STATUS AND INFORMATION REGISTERS
A set of four registers--status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status register (SSR)--contains information about the DS21Q50 framer's real-time status When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers sets to 1. The bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are not latched. This means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, it remains set until the user reads that bit. The bit is cleared when it is read and it is not set again until the event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit remains set if the alarm is still present). The user always precedes a read of the SR1, SR2, and RIR registers with a write. The byte written to the register informs the framer which bits the user wishes to read and have cleared. The user writes a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register is updated with the latest information. When a 0 is written to a bit position, the read register is not updated and the previous value is held. A write to the status and information registers is immediately followed by a read of the same register. The read result should be logically ANDed with the mask byte that was just written and this value should be written back into the same register to ensure that bit clears. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access through the parallel port. The write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21Q50 with higher order software languages. The SSR register operates differently than the other three. It is a read-only register and reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write. The SR1and SR2 registers can initiate a hardware interrupt through the INT output pin. Each of the alarms and events in SR1 and SR2 can be either masked or unmasked from the interrupt pin through the interrupt mask register 1 (IMR1) and interrupt mask register 2 (IMR2). The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, and RCMF). The alarm-caused interrupts force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 5-1). The INT pin is allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event-based interrupts force the INT pin low when the event occurs. The INT pin returns high () when the user reads the event bit that caused the interrupt to occur. Furthermore, some event-based interrupts occur continuously as long as the event is occurring (RSLIP, SEC, TMF, RMF, TAF, RAF, RCMF). Other event-based interrupts force the INT pin low only once when the event is first detected (LOTC, PRSBD, RDMA, RSA1, RSA0), i.e., the PRBSD interrupt fires once when the receiver detects the PRBS pattern. If the receiver continues to receive the PRBS pattern, no more interrupts fire. If the receiver then detects that PRBS is no longer being sent, the receiver resets and when it receives the PRBS pattern again, another interrupt fires.
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Register Name: Register Description: Register Address: Bit Name 7 RGM1 BIT 7 6 5 4 3 2 1 0
RIR Receive Information Register 08 Hex 6 RGM0 5 JALT 4 RESF 3 RESE 2 CRCRC 1 FASRC 0 CASRC
NAME RGM1 RGM0 JALT RESF RESE CRCRC FASRC CASRC
FUNCTION Receive Gain Monitor Bit 1. See the Level Indication table below for level indication. Receive Gain Monitor Bit 0. See the Level Indication table below for level indication. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of its limit; useful for debugging jitter attenuation operation. Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame is deleted. Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame is repeated. CRC Resync Criteria Met. Set when 915/1000 codewords are received in error. FAS Resync Criteria Met. Set when three consecutive FAS words are received in error. CAS Resync Criteria Met. Set when two consecutive CAS MF alignment words are received in error.
LEVEL INDICATION
RGM1 0 0 1 1 RGM0 0 1 0 1 LEVEL (dB) 0 to 10 10 to 20 20 to 30 >30
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Register Name: Register Description: Register Address: Bit Name NAME CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA 7 CSC5 BIT 7 6 5 4 3 2 1 0
SSR Synchronizer Status Register 09 Hex 6 CSC4 5 CSC3 4 CSC2 3 CSC0 2 FASSA 1 CASSA 0 CRC4SA
FUNCTION CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CRC4 Sync Counter Bit 4 CRC4 Sync Counter Bit 3 CRC4 Sync Counter Bit 2 CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter Bit 1 is not accessible. FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word.
5.1 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. Disabling the CRC4 mode (CCR1.0 = 0) can also clear the counter. This counter determines the time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, the search should be abandoned and proper action taken. The CRC4 sync counter rolls over.
Table 5-1. Alarm Criteria
ALARM RSA1 (receive signaling all ones) RSA0 (receive signaling all zeros) RDMA (receive distant multiframe alarm) RUA1 (receive unframed all ones) RRA (receive remote alarm) RCL (receive carrier loss) SET CRITERIA Over 16 consecutive frames (one full MF) time slot 16 contains fewer than three 0s Over 16 consecutive frames (one full MF) time slot 16 contains all 0s Bit 6 in time slot 16 of frame 0 set to one for two consecutive MF Fewer than three 0s in two frames (512 bits) Bit 3 of nonalign frame set to 1 for three consecutive occasions 255 (or 2048) consecutive 0s received CLEAR CRITERIA Over 16 consecutive frames (one full MF) time slot 16 contains three or more 0s Over 16 consecutive frames (one full MF) time slot 16 contains at least a single 1 Bit 6 in time slot 16 of frame 0 set to 0 for two consecutive MF More than two 0s in two frames (512 bits) Bit 3 of nonalign frame set to 0 for three consecutive occasions In 255-bit times, at least 32 1s are received ITU SPEC G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1.6.1.2 O.162 2.1.4 G.775/ G.962
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Register Name: Register Description: Register Address: Bit Name NAME RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS 7 RSA1 BIT 7 6 5 4 3 2 1 0
SR1 Status Register 1 0A Hex 6 RDMA 5 RSA0 4 RSLIP 3 RUA1 2 RRA 1 RCL 0 RLOS
FUNCTION Receive Signaling All Ones. Set when the contents of time slot 16 contain fewer than three 0s over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. RSA1 and RSA0 are set if a change in signaling is detected. Receive Distant MF Alarm. Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. Receive Signaling All Zeros. Set when over a full MF, time slot 16 contains all zeros. RSA1 and RSA0 are set if a change in signaling is detected. Receive Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data. Receive Unframed All Ones. Set when an unframed all-ones code is received at RPOSI and RNEGI. Receive Remote Alarm. Set when a remote alarm is received at RPOSI and RNEGI. Receive Carrier Loss. Set when 255 (or 2048 if CCR2.1 = 1) consecutive 0s have been detected at RTIP and RRING. Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream.
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Register Name: Register Description: Register Address: Bit Name NAME RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS 7 RSA1 BIT 7 6 5 4 3 2 1 0
IMR1 Interrupt Mask Register 1 18 Hex 6 RDMA 5 RSA0 4 RSLIP 3 RUA1 FUNCTION Receive Signaling All Ones 0 = interrupt masked 1 = interrupt enabled Receive Distant MF Alarm 0 = interrupt masked 1 = interrupt enabled Receive Signaling All Zeros 0 = interrupt masked 1 = interrupt enabled Receive Elastic Store Slip Occurrence 0 = interrupt masked 1 = interrupt enabled Receive Unframed All Ones 0 = interrupt masked 1 = interrupt enabled Receive Remote Alarm 0 = interrupt masked 1 = interrupt enabled Receive Carrier Loss 0 = interrupt masked 1 = interrupt enabled Receive Loss of Sync 0 = interrupt masked 1 = interrupt enabled 2 RRA 1 RCL 0 RLOS
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Register Name: Register Description: Register Address: Bit Name NAME RMF RAF TMF SEC TAF LOTC RCMF PRBSD 7 RMF BIT 7 6 5 4 3 2 1 0
SR2 Status Register 2 0B Hex 6 RAF 5 TMF 4 SEC 3 TAF 2 LOTC FUNCTION Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Receive Align Frame. Set every 250s at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Transmit Multiframe. Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. One-Second Timer. Set on increments of one second based on RCLK. If CCR2.7 = 1, this bit is set every 62.5ms instead of once a second. Transmit Align Frame. Set every 250s at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Loss-of-Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3.9ms). Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; continues to be set every 2ms on an arbitrary boundary if CRC4 is disabled. Pseudorandom Bit-Sequence Detect. When receive PRBS is enabled, this bit is set when the 215 - 1 PRBS pattern is detected at RPOS and RNEG. The PRBS pattern can be framed, unframed, or in a specific time slot. 1 RCMF 0 PRBSD
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Register Name: Register Description: Register Address: Bit Name NAME RMF RAF TMF SEC TAF LOTC RCMF PRBSD 7 RMF BIT 7 6 5 4 3 2 1 0
IMR2 Interrupt Mask Register 2 19 Hex 6 RAF 5 TMF 4 SEC 3 TAF FUNCTION Receive CAS Multiframe 0 = interrupt masked 1 = interrupt enabled Receive Align Frame 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe 0 = interrupt masked 1 = interrupt enabled One-Second Timer 0 = interrupt masked 1 = interrupt enabled Transmit Align Frame 0 = interrupt masked 1 = interrupt enabled Loss-of-Transmit Clock 0 = interrupt masked 1 = interrupt enabled Receive CRC4 Multiframe 0 = interrupt masked 1 = interrupt enabled Pseudorandom Bit-Sequence Detect 0 = interrupt masked 1 = interrupt enabled 2 LOTC 1 RCMF 0 PRBSD
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6. ERROR COUNT REGISTERS
A set of four counters in each transceiver of the DS21Q50 record bipolar (BPV) or code violations (CV), errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The Ebit counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.7 = 1), as determined by the timer in status register 2 (SR2.4). Hence, these registers contain performance data from either the previous second or the previous 62.5ms. The user can use the interrupt from the one-second timer to determine when to read these registers. The user has a full second (or 62.5ms) to read the counters before the data is lost. The counters saturate at their respective maximum counts and do not roll over.
6.1 BPV or Code Violation Counter
Violation count register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit counter that records either BPVs or CVs. If CCR2.6 = 0, the VCR counts BPVs. BPVs are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receiver through CCR1.2, HDB3 codewords are not counted as BPVs. If CCR2.6 = 1, the VCR counts CVs, as defined in ITU O.161. CVs are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss-of-sync conditions. The counter saturates at 65,535 and does not roll over. The bit error rate on an E1 line would have to be greater than 10-2 before the VCR would saturate.
Register Name: Register Description: Register Address: Bit Name Name NAME V15 V0 7 V15 V7 VCR1, VCR2 Bipolar Violation Count Registers 00 Hex, 01 Hex 6 V14 V6 BIT VCR1.7 VCR2.0 5 V13 V5 4 V12 V4 3 V11 V3 2 V10 V2 1 V9 V1 0 V8 V0
FUNCTION MSB of the 16-bit code violation count LSB of the 16-bit code violation count
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6.2 CRC4 Error Counter
CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. CRCCR1 and CRCCR2 have alternate functions.
Register Name: Register Description: Register Address: Bit Name Name 7 CRC15 CRC7 CRCCR1, CRCCR2 CRC4 Count Registers 02 Hex, 03 Hex 6 CRC14 CRC6 BIT CRCCR1.7 CRCCR2.0 5 CRC13 CRC5 4 CRC12 CRC4 3 CRC11 CRC/3 2 CRC10 CRC2 1 CRC9 CRC1 0 CRC8 CRC0
NAME CRC15 CRC0
FUNCTION MSB of the 16-bit CRC4 error count LSB of the 16-bit CRC4 error count
6.3 E-Bit/PRBS Bit Error Counter
E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE), as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function is enabled. In this mode, the counter is active when the receive PRBS detector can synchronize to the PRBS pattern. This pattern can be framed, unframed, or in any time slot. See Section 8 for more details.
Register Name: Register Description: Register Address: Bit Name Name NAME EB15 EB0 7 EB15 EB7 EBCR1, EBCR2 E-Bit Count Registers 04 Hex, 05 Hex 6 EB14 EB6 BIT EBCR1.7 EBCR2.0 5 EB13 EB5 4 EB12 EB4 3 EB11 EB3 2 EB10 EB2 1 EB9 EB1 0 EB8 EB0
FUNCTION MSB of the 16-bit E-bit error count LSB of the 16-bit E-bit error count
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6.4 FAS Error Counter
FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit counter that records word errors in the frame alignment signal (FAS) in time slot 0. This counter is disabled when RLOS is high. FAS errors are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FASword error count in a one-second period is 4000, this counter cannot saturate.
Register Name: Register Description: Register Address: Bit Name Name 7 FAS15 FAS7 FASCR1, FASCR2 FAS Error Count Registers 06 Hex, 07 Hex 6 FAS14 FAS6 BIT FASCR1.7 FASCR2.0 5 FAS13 FAS5 4 FAS12 FAS4 3 FAS11 FAS3 2 FAS10 FAS2 1 FAS9 FAS1 0 FAS8 FAS0
NAME FAS15 FAS0
FUNCTION MSB of the 16-bit FAS error count LSB of the 16-bit FAS error count
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7. DS0 MONITORING FUNCTION
Each DS21Q50 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0-RCM4 bits in the CCR4 register need to be properly set. The DS0 channel pointed to by the TCM0-TCM4 bits appear in the transmit DS0 monitor (TDS0M) register; the DS0 channel pointed to by the RCM0-RCM4 bits appear in the receive DS0 (RDS0M) register. The TCM4- TCM0 and RCM4-RCM0 bits should be programmed with the decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction need to be monitored, the following values are programmed into CCR4 and CCR5: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1
Register Name: Register Description: Register Address: Bit Name NAME RLB LLB LIAIS TCM4 TCM3 TCM2 TCM1 TCM0 7 RLB BIT 7 6 5 4 3 2 1 0 Remote Loopback Local Loopback Line Interface AIS Generation Enable Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data appears in the TDS0M register. See Section 6 or details. Transmit Channel Monitor Bit 3 Transmit Channel Monitor Bit 2 Transmit Channel Monitor Bit 1 Transmit Channel Monitor Bit 0. LSB of the channel decode.
RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
CCR3 (Repeated here from Section 3 for convenience.) Common Control Register 3 14 Hex 6 LLB 5 LIAIS 4 TCM4 3 TCM3 2 TCM2 1 TCM1 0 TCM0
FUNCTION
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Register Name: Register Description: Register Address: Bit Name NAME B1 B2 B3 B4 B5 B6 B7 B8 7 B1 BIT 7 6 5 4 3 2 1 0
TDS0M Transmit Ds0 Monitor Register 22 Hex 6 B2 5 B3 4 B4 3 B5 FUNCTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2 Transmit DS0 Channel Bit 3 Transmit DS0 Channel Bit 4 Transmit DS0 Channel Bit 5 Transmit DS0 Channel Bit 6 Transmit DS0 Channel Bit 7 Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted). 2 B6 1 B7 0 B8
Register Name: Register Description: Register Address: Bit Name NAME LIRST RESA RESR RCM4 RCM3 RCM2 RCM1 RCM0 7 LIRST BIT 7 6 5 4 3 2 1 0
CCR4 (Repeated here from Section 3 for convenience.) Common Control Register 4 15 Hex 6 RESA 5 RESR 4 RCM4 3 RCM3 2 RCM2 1 RCM1 0 RCM0
FUNCTION Line Interface Reset Receive Elastic Store Align Receive Elastic Store Reset Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data appears in the RDS0M register. See Section 6 or details. Receive Channel Monitor Bit 3 Receive Channel Monitor Bit 2 Receive Channel Monitor Bit 1 Receive Channel Monitor Bit 0. LSB of the channel decode.
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Register Name: Register Description: Register Address: Bit Name NAME B1 B2 B3 B4 B5 B6 B7 B8 7 B1 BIT 7 6 5 4 3 2 1 0
RDS0M Receive Ds0 Monitor Register 2A Hex 6 B2 5 B3 4 B4 3 B5 FUNCTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). Receive DS0 Channel Bit 2 Receive DS0 Channel Bit 3 Receive DS0 Channel Bit 4 Receive DS0 Channel Bit 5 Receive DS0 Channel Bit 6 Receive DS0 Channel Bit 7 Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit received). 2 B6 1 B7 0 B8
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8. PRBS GENERATION AND DETECTION
The DS21Q50 can transmit and receive the 215 - 1 PRBS pattern. This PRBS pattern complies with ITUT O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0), or in any single time slot. Register CCR5 contains the control bits for configuring the transmit and receive PRBS functions. Table 8-1 and Table 8-2 show the selection criteria for transmit and receive operation modes. In transmit and receive mode 1 operation, the transmit and receive channelmonitor select bits of registers CCR3 and CCR4 have an alternate use. When these modes are selected, those bits determine which time slots transmit and/or receive the PRBS pattern. SR2.0 indicates when the receiver has synchronized to the PRBS pattern. The PRBS synchronizer remains in sync until it experiences 6-bit errors or more within a 64-bit span. Choosing any receive mode other than NORMAL causes the 16-bit E-bit error counter--EBCR1 and EBCR2--to be reconfigured for counting PRBS errors. User-definable outputs OUTA or OUTB can be configured to output a pulse for every bit error received. See Section 15 and Table 15-1 for details. This signal can be used with external circuitry to track bit error rates during PRBS testing. Once synchronized, any bit errors received cause a positive-going pulse, synchronous with RCLK.
Table 8-1. Transmit PRBS Mode Select
TPRBS1 (CCR5.3) 0 0 1 1 TPBRS0 (CCR5.2) 0 1 0 1 MODE Mode 0: Normal (PRBS disabled) Mode 1: PRBS in TSx. PRBS pattern is transmitted in a single time slot (TS). In this mode, the transmit channel-monitor select bits in register CCR3 are used to select a time slot in which to transmit the PRBS pattern. Mode 2: PRBS in all but TS0. PRBS pattern is transmitted in time slots 1 through 31. Mode 3: PRBS unframed. PRBS pattern is transmitted in all time slots.
Table 8-2. Receive PRBS Mode Select
RPRBS1 (CCR5.1) 0 0 1 1 RPBRS0 (CCR5.0) 0 1 0 1 MODE Mode 0: Normal (PRBS disabled) Mode 1: PRBS in TSx. PRBS pattern is received in a single time slot (TS). In this mode, the receive channel-monitor select bits in register CCR4 are used to select a time slot in which to receive the PRBS pattern. Mode 2: PRBS in all but TS0. PRBS pattern is received in time slots 1 through 31. Mode 3: PRBS unframed. PRBS pattern is received in all time slots.
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9. SYSTEM CLOCK INTERFACE
A single system clock interface (SCI) is common to the four DS21Q50 transceivers. The SCI allows any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q50s are used to build an N port system, the SCI allows any one of the N ports to be the master. The selected reference is then distributed to the other DS21Q50s through the REFCLK pin. The REFCLK pin acts as an output on the DS21Q50, which has been selected to provide the reference clock from one of its four receivers. On DS21Q50s not selected to source the reference clock, this pin becomes an input by writing 0s to the SCSx bits. The reference clock is also passed to the clock synthesizer PLL to generate a 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. This clock can then be used with the IBO function to merge up to eight E1 lines onto a single high-speed PCM bus. If the master E1 port fails (enters a receive carrier-loss condition), that port automatically switches to the clock present on the MCLK pin. Therefore, MCLK acts as the backup source of master clock. The host can then find and select a functioning E1 port as the master. Because the selected port's clock is passed to the other DS21Q50s in a multiple device configuration, one DS21Q50's synthesizer can always be the source of the high-speed clock. This allows smooth transitions when clock-source switching occurs. The SCI control register exists in transceiver 1 only (TS0, TS1 = 0).
Register Name: Register Description: Register Address: Bit Name 7 AJACKE BIT 7 6 SCICR System Clock Interface Control Register (Note: This register is valid only for transceiver 1 (TS0 = 0, TS1 = 0). 1D Hex 6 BUCS 5 SOE 4 CSS1 3 CSS0 2 SCS2 1 SCS1 0 SCS0
NAME AJACKE BUCS
FUNCTION AJACK Enable. This bit enables the alternate jitter attenuator. Backup Clock Select. Selects which clock source to switch to automatically during a lossof-transmit clock event. 0 = During an LOTC event, switch to MCLK 1 = During an LOTC event, switch to system reference clock Synthesizer Output Enable 0 = 2/4/8/16MCK pin in high-Z mode 1 = 2/4/8/16MCK pin active Clock Synthesizer Select Bit 1 (Table 9-2) Clock Synthesizer Select Bit 0 (Table 9-2) System Clock Select Bit 2 (Table 9-1) System Clock Select Bit 1 (Table 9-1) System Clock Select Bit 0 (Table 9-1)
SOE CSS1 CSS0 SCS2 SCS1 SCS0
5 4 3 2 1 0
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Table 9-1. Master Port Selection
SCS2 0 0 0 0 1 1 1 1 SCS1 0 0 1 1 0 0 1 1 SCS0 0 1 0 1 0 1 0 1 PORT SELECTED AS MASTER None (Master Port can be derived from another DS21Q50 in the system.) Transceiver 1 Transceiver 2 Transceiver 3 Transceiver 4 Reserved for future use Reserved for future use Reserved for future use
Table 9-2. Synthesizer Output Select
CSS1 0 0 1 1 CSS0 0 1 0 1 SYNTHESIZER OUTPUT FREQUENCY (MHz) 2.048 4.096 8.192 16.384
10.
TRANSMIT CLOCK SOURCE
Depending on the operating mode, the transmit clock can be derived from different sources. In a basic configuration, where the IBO function is disabled, the transmit clock is normally sourced from the TCLK pin. In this mode, a 2.048MHz clock with 50ppm accuracy is applied to the TCLK pin. If the signal at TCLK is lost, the DS21Q50 automatically switches to either the system reference clock present on the REFCLK pin or to the recovered clock off the same port, depending on which source the host assigned as the backup clock. At the same time the host can be notified of the loss-of-transmit clock through an interrupt. The host can at any time force a switchover to one of the two backup clock sources, regardless of the state of the TCLK pin. When the IBO function is enabled, the transmit clock must be synchronous to the system clock, since slips are not allowed in the transmit direction. In this mode, the TCLK pin is ignored and a transmit clock is automatically provided by the IBO circuit by dividing the clock present on the SYSCLK pin by 2, 4, or 8. In this configuration, if the signal present on the SYSCLK pin is lost, the DS21Q50 automatically switches to either the system reference clock or to the recovered clock off the same port, depending on which source the host assigned as the backup clock. The host can at any time force a switchover to one of the two backup clock sources, regardless of the state of the SYSCLK pin.
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11.
IDLE CODE INSERTION
The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code placed in the transmit idle-definition register (TIDR). This allows the same 8-bit code to be placed into any of the 32 E1 channels. Each of the bit positions in the TIRs represents a DS0 channel in the outgoing frame. When these bits are set to 1, the corresponding channel transmits the idle code contained in the TIDR.
Register Name: Register Description: Register Address: Bit Name Name Name Name 7 CH8 CH16 CH24 CH32 TIR1, TIR2, TIR3, TIR4 Transmit Idle Registers 24 Hex, 25 Hex, 26 Hex, 27 Hex 6 CH7 CH15 CH23 CH31 BIT TIR1.0 to 4.7 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25
NAME CH1 to CH32
FUNCTION Transmit Idle Code-Insertion Control Bits 0 = do not insert the idle code in the TIDR into this channel 1 = insert the idle code in the TIDR into this channel
Register Name: Register Description: Register Address: Bit Name 7 TIDR7
TIDR Transmit Idle Definition Register 23 Hex 6 TIDR6 5 TIDR5 4 TIDR4 3 TIDR3 2 TIDR2 1 TIDR1 0 TIDR0
NAME TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0
BIT 7 6 5 4 3 2 1 0
FUNCTION MSB of the idle code (this bit is transmitted first)
LSB of the idle code (this bit is transmitted last)
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12.
PER-CHANNEL LOOPBACK
The DS21Q50 has per-channel loopback capability that can operate in one of two modes: remote perchannel loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which channels (if any) in the transmit direction should be replaced with the data from the receiver or, rather, off the E1 line. In local per-channel loopback mode, PCLB1/2/3/4 determines which channels (if any) in the receive direction should be replaced with the data from the transmit direction. If either mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. There are no restrictions on which channels can be looped back or on how many channels can be looped back.
Register Name: Register Description: Register Address: Bit # Name Name Name Name 7 CH8 CH16 CH24 CH32 PCLB1, PCLB2, PCLB3, PCLB4 Per-Channel Loopback Registers 2B Hex, 2C Hex, 2D Hex, 2E Hex 6 CH7 CH15 CH23 CH31 BIT PCLB1.0 to 4.7 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25
NAME CH1 to CH32
FUNCTION Per-Channel Loopback Control Bits 0 = do not loopback this channel 1 = loopback this channel
13.
ELASTIC STORE OPERATION
The DS21Q50 contains a two-frame (512 bits) elastic store for the receive direction. The elastic store is used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not frequency locked) backplane clock that can be 2.048MHz for normal operation or 4.096MHz, 8.192MHz, or 16.384MHz when using the IBO. The elastic store contains full-controlled slip capability. If the receive elastic store is enabled (RCR.4 = 1), the user must provide a 2.048MHz clock to the SYSCLK pin. If the IBO function is enabled, a 4.096MHz, 8.192MHz, or 16.384MHz clock must be provided at the SYSCLK pin. The user can either provide a frame/multiframe sync at the RSYNC pin (RCR.5 = 1) or have the RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5 = 0). If the user wishes to obtain pulses at the frame boundary, RCR1.6 must be set to 0. If the user wishes to have pulses occur at the multiframe boundary, RCR1.6 must be set to 1. If the elastic store is enabled, either CAS (RCR.7 = 0) or CRC4 (RCR.7 = 1) multiframe boundaries are indicated through the RSYNC output. See Section 19.1 for timing details. If the 512-bit elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of data (256 bits) is repeated at RSER, and the SR1.4 and RIR.3 bits are set to 1. If the buffer fills, a full frame of data is deleted, and the SR1.4 and RIR.4 bits are set to 1.
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14.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
On the receiver, the RAF and RNAF registers always report the data as it is received in the additional (Sa) and international (Si) bit locations. The RAF and RNAF registers are updated with the setting of the receive align frame bit in status register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250ms to retrieve the data before it is lost. On the transmitter, data is sampled from the TAF and TNAF registers with the setting of the transmit align frame bit in status register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and TNAF registers. It has 250s to update the data or else the old data is retransmitted. Data in the Si bit position is overwritten if either the framer is programmed (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) to have automatic E-bit insertion enabled. Data in the Sa-bit position is overwritten if any of the TCR.3 to TCR.7 bits is set to 1. Please see the register descriptions for TCR for more details.
Register Name: Register Description: Register Address: Bit Name NAME Si 0 0 1 1 0 1 1 7 Si BIT 7 6 5 4 3 2 1 0 International Bit Frame Alignment Signal Bit Frame Alignment Signal Bit Frame Alignment Signal Bit Frame Alignment Signal Bit Frame Alignment Signal Bit Frame Alignment Signal Bit Frame Alignment Signal Bit 6 0 RAF Receive Align Frame Register 28 Hex 5 0 4 1 3 1 FUNCTION 2 0 1 1 0 1
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Register Name: Register Description: Register Address: Bit Name NAME Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 7 Si BIT 7 6 5 4 3 2 1 0
RNAF Receive Nonalign Frame Register 29 Hex 6 1 5 A 4 Sa4 3 Sa5 FUNCTION International Bit Frame Nonalignment Signal Bit Remote Alarm Additional Bit 4 Additional Bit 5 Additional Bit 6 Additional Bit 7 Additional Bit 8 2 Sa6 1 Sa7 0 Sa8
Register Name: Register Description: Register Address:
TAF Transmit Align Frame Register 20 Hex
(Must be programmed with the 7-bit FAS word; the DS21Q50 does not automatically set these bits.)
Bit Name NAME Si 0 0 1 1 0 1 1
7 Si BIT 7 6 5 4 3 2 1 0
6 0
5 0
4 1
3 1 FUNCTION
2 0
1 1
0 1
International Bit Frame Alignment Signal Bit. Set this bit = 0. Frame Alignment Signal Bit. Set this bit = 0. Frame Alignment Signal Bit. Set this bit = 1. Frame Alignment Signal Bit. Set this bit = 1. Frame Alignment Signal Bit. Set this bit = 0. Frame Alignment Signal Bit. Set this bit = 1. Frame Alignment Signal Bit. Set this bit = 1.
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Register Name: Register Description: Register Address:
TNAF Transmit Nonalign Frame Register 21 Hex
(Bit 6 must be programmed to 1; the DS21Q50 does not automatically set this bit.)
Bit Name NAME Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
7 Si BIT 7 6 5 4 3 2 1 0
6 1
5 A
4 Sa4
3 Sa5 FUNCTION
2 Sa6
1 Sa7
0 Sa8
International Bit Frame Nonalignment Signal Bit. Set this bit = 1. Remote Alarm (used to transmit the alarm) Additional Bit 4 Additional Bit 5 Additional Bit 6 Additional Bit 7 Additional Bit 8
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15.
USER-CONFIGURABLE OUTPUTS
There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, logic 0 and 1 levels to control external circuitry, or access transmit data between the framer and transmit line interface unit. OUTA and OUTB can be active low or active high when operating as clock and alarm outputs. OUTA is active high if OUTAC.4 =1 and active low if OUTAC.3 = 0. OUTB is active high if OUTBC.4 = 1 and active low if OUTBC.4 = 0 (Table 15-1). Mode 0000 is selected for controlling external circuitry. In this configuration, the OUTA pin follows OUTAC.4 and the OUTB pin follows OUTBC.4. The OUTAC register also contains a control bit for CMI operation. See Section 16 for details about CMI operation.
Register Name: Register Description: Register Address: Bit Name 7 TTLIE BIT 7 6 5 4 3 2 1 0 OUTAC OUTA Control Register 1A Hex 6 CMII 5 CMIE 4 OA4 3 OA3 2 OA2 1 OA1 0 OA0
NAME TTLIE CMII CMIE OA4 OA3 OA2 OA1 OA0
FUNCTION TTL Input Enable. When this bit is set, the receiver can accept TTL positive and negative data at the RTIP and RRING inputs. The data is clocked in on the falling edge of MCLK. CMI Invert. See Section 17 for details. 0 = CMI input data not inverted 1 = CMI input data inverted CMI Enable. See Section 17 for details. 0 = CMI disabled 1 = CMI enabled OUTA Control Bit 4. Inverts OUTA output. OUTA Control Bit 3 (Table 15-1) OUTA Control Bit 2 (Table 15-1) OUTA Control Bit 1 (Table 15-1) OUTA Control Bit 0 (Table 15-1)
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Register Name: Register Description: Register Address: Bit Name 7 NRZE BIT
OUTBC OUTB Control Register 1B Hex 6 -- 5 -- 4 OB4 3 OB3 2 OB2 FUNCTION NRZ Enable. When this bit is set, the receiver can accept TTL-type NRZ data at the RTIP input. RRING becomes a clock input. 0 = RTIP and RRING are in normal mode 1 = RTIP becomes an NRZ TTL type input and RRING is its associated clock input. Data at RTIP is clocked in on the falling edge of the clock present on RRING. Unused. Should be set = 0 for proper operation. Unused. Should be set = 0 for proper operation. OUTB Control Bit 4. Inverts OUTB output. OUTB Control Bit 3 OUTB Control Bit 2 OUTB Control Bit 1 OUTB Control Bit 0 1 OB1 0 OB0
NAME
NRZE
7
-- -- OB4 OB3 OB2 OB1 OB0
6 5 4 3 2 1 0
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Table 15-1. OUTA and OUTB Function Select
OA3 OB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OA2 OB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OA1 OB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OA0 OB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION External Hardware Control Bit. In this mode, OUTA and OUTB can be used as simple control pins for external circuitry. Use OA4 and OB4 to toggle OUTA and OUTB. Receive Recovered Clock, RCLK Receive Loss-of-Sync Indicator. Real-time hardware version of SR1.0 (Table 5-1) Receive Loss Of Carrier Indicator. Real-time hardware version of SR1.1 (Table 5-1) Receive Remote Alarm Indicator. Real-time hardware version of SR1.2 (Table 5-1) Receive Unframed All Ones Indicator. Real-time hardware version of SR1.3 (Table 5-1) Receive Slip Occurrence Indicator. One-clock-wide pulse for every slip of the receive elastic store. Hardware version of SR1.4. Receive CRC Error Indicator. One-clock-wide pulse for every multiframe that contains a CRC error. Output forced to 0 during loss of sync. Loss Of Transmit Clock Indicator. Real-time hardware version SR2.2 (Table 5-1) RFSYNC. Recovered frame-sync pulse. PRBS Bit Error. A half-clock-wide pulse for every bit error in the received PRBS pattern. TDATA/RDATA OUTB outputs an NRZ version of the transmit data stream (TDATA) prior to the transmit line interface. OUTA outputs the received serial data stream (RDATA) prior to the elastic store. Receive CRC4 Multiframe Sync. Recovered CRC4 MF sync pulse. Receive CAS Multiframe Sync. Recovered CAS MF sync pulse. Transmit Current Limit. Real-time indicator that the TTIP and TRING outputs have reached their 50mA current limit. TPOS/TNEG Output. This mode outputs the AMI/HDB3 encoded transmit data. OUTA outputs TNEG data. OUTB outputs TPOS data.
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16.
LINE INTERFACE UNIT
The line interface unit in the DS21Q50 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR), described below, controls each of these three sections.
Register Name: Register Description: Register Address: Bit Name NAME L2 L1 L0 EGL JAS JABDS DJA TPD 7 L2 BIT 7 6 5 4 3 2 1 0 LICR Line Interface Control Register 17 Hex 6 L1 5 L0 4 EGL 3 JAS 2 JABDS 1 DJA 0 TPD
FUNCTION Line Build-Out Select Bit 2. Sets the transmitter build-out. Line Build-Out Select Bit 1. Sets the transmitter build-out. Line Build-Out Select Bit 0. Sets the transmitter build-out. Receive Equalizer Gain Limit 0 = -12dB 1 = -43dB Jitter Attenuator Select 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) Disable Jitter Attenuator 0 = jitter attenuator enabled 1 = jitter attenuator disabled Transmit Power-Down 0 = powers down the transmitter and three-states the TTIP and TRING pins 1 = normal transmitter operation
16.1 Receive Clock and Data Recovery
The DS21Q50 contains a digital clock-recovery system. See Figure 1-1 and Figure 16-2 for more details. The device couples to the receive E1 shielded twisted pair or coax through a 1:1 transformer (Table 16-4). The 2.048MHz clock attached at the MCLK pin is internally multiplied by 16 through an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance (Figure 16-5). Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs, and the RCLK is sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, RCLK can exhibit slightly shorter high cycles of the clock. This is because of the highly oversampled digital clock-recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. See the Receive AC Characteristics in Section 21.4 for more details.
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16.2 Termination
The DS21Q50 is designed to be fully software-selectable for 75W and 120W termination without the need to change any external resistors. The user can configure the DS21Q50 for 75W or 120W receive termination by setting the IRTSEL (CCR5.4) bit. When using the internal termination feature, the external termination resistance should be 120W (typically two 60W resistors). Setting IRTSEL = 1 causes the DS21Q50 to internally apply parallel resistance to the external resistors in order to adjust the termination to 75W. See Figure 16-3 for details.
16.3 Receive Monitor Mode
When connecting to a monitor port, a large resistive loss is incurred due to the voltage divider between the E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm) as shown in Figure 16-1. The four receivers of the DS21Q50 can provide gain to overcome the resistive loss of a monitor connection. This is typically a purely resistive loss/gain and should not be confused with the cable loss characteristics of an E1 transmission line. By setting the receive monitor mode register as shown in Table 16-1, the receiver can be programmed to provide 30dB of gain.
Figure 16-1. Typical Monitor Port Application
PRIMARY E1 TERMINATING DEVICE Rm X F M R
E1 LINE
Rm
Rt DS21Q50
MONITOR PORT JACK
SECONDARY TERMINATING DEVICE
Table 16-1. Receive Monitor Mode Gain
MONITOR MODE (ADDRESS = 1Fh) REGISTER VALUE 70h 00h GAIN (dB) 30 0
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Register Name: Register Description: Register Address: Bit Name NAME -- MM2 MM1 MM0 -- -- -- -- 7 0 BIT 7 6 5 4 3 2 1 0
RMM Receive Monitor Mode Register 1F Hex 6 MM1 5 MM1 4 MM0 3 0 2 0 1 0 0 0
FUNCTION Reserved. Must be set = 0 for proper operation Monitor Mode 2. Sets the internal linear gain boost (dB) for monitor mode applications. Please refer to the table below for proper settings. Monitor Mode 1. Sets the internal linear gain boost (dB) for monitor mode applications. Please refer to the table below for proper settings. Monitor Mode 0. Sets the internal linear gain boost (dB) for monitor mode applications. Please refer to the table below for proper settings. Reserved. Must be set = 0 for proper operation Reserved. Must be set = 0 for proper operation Reserved. Must be set = 0 for proper operation Reserved. Must be set = 0 for proper operation
Table 16-2. Monitor Mode Settings
MM2 0 0 0 0 1 1 1 1 MM1 0 0 1 1 0 0 1 1 MM0 0 1 0 1 0 1 0 1 INTERNAL LINEAR GAIN BOOST Normal Operation (no boost) Unused Unused Unused Unused Unused Unused 30dB
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16.4 Transmit Waveshaping and Line Driving
The DS21Q50 uses a set of laser-trimmed delay lines with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications (Figure 16-4). The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in the LICR. The DS21Q50 can be set up in a number of various configurations, depending on the application (Table 16-3).
Table 16-3. Line Build-Out Select in LICR
L2 0 0 0 0 1 L1 0 0 1 1 0 L0 0 1 0 1 0 APPLICATION 75W normal 120W normal 75W with protection resistors 120W with protection resistors 75W with high return loss TRANSFORMER 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up RETURN LOSS* NM NM NM NM 21dB RT**() 0 0 2.5 2.5 6.2
*NM = Not Meaningful (return loss value too low for significance). **Refer to Application Note 336: Transparent Operation on T1, E1 Framers and Transceivers for details on E1 line interface design.
Because of DS21Q50 transmitter's design, very little jitter (less than 0.005 UIP-P broadband from 10Hz to 100kHz) is added to the jitter present on TCLK (or source used for transmit clock). The waveform created is independent of the duty cycle of TCLK. The transmitter in the device couples to the E1 transmitshielded twisted pair or coax through a 1:2 step-up transformer, as shown in Figure 16-2. For the devices to create the proper waveforms, the transformer must meet the specifications listed in Table 16-4. The line driver in the device contains a current limiter that prevents more than 50mA (RMS) from being sourced in a 1 load.
Table 16-4. Transformer Specifications
SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Intertwining Capacitance DC Resistance RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) 3% 600mH minimum 1.0mH maximum 40pF maximum 1.2W maximum
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Figure 16-2. External Analog Connections (Basic Configuration)
0.47mF
(NONPOLARIZED)
1/4 DS21Q50
0.1mF TTIP TRING DVDD DVSS RVDD RVSS RTIP RRING TVDD TVSS MCLK 0.01mF
+3.3V
E1 TRANSMIT LINE 2:1 1:1 E1 RECEIVE LINE
Rr 0.1mF Rr
0.1mF
0.1mF
2.048MHz
Figure 16-3. External Analog Connections (Protected Interface)
+VDD D2
Fuse
2:1
S
D1
+VDD
TRANSMIT LINE
Fuse
TTIP1
0.47mF (non polarized)
C1 D4
DVDD DVSS RVDD RVSS TVDD TVSS
0.1mF 0.01mF 0.1mF
TRING1
68mF
D3
0.1mF
+VDD
Fuse
1:1
S
D5
D6
1/4 DS21Q50
RTIP1
RECEIVE LINE
Fuse
C2 60 D7 D8
RRING1
MCLK
2.048MHz
60
0.1mF
NOTE 1: ALL RESISTOR VALUES ARE 1%. NOTE 2: C1 = C2 = 0.1m. NOTE 3: S IS A 6V TRANSIENT SUPPRESSOR. NOTE 4: D1 TO D8 ARE SCHOTTKY DIODES. NOTE 5: THE FUSES ARE OPTIONAL TO PREVENT AC POWER-LINE CROSSES FROM COMPROMISING THE TRANSFORMERS. NOTE 6: THE 68mF IS USED TO KEEP THE LOCAL POWER-PLANE POTENTIAL WITHIN TOLERANCE DURING A SURGE.
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Figure 16-4. Transmit Waveform Template
1.2 1.1 1.0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 Template
TIME (ns)
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16.5 Jitter Attenuators
The DS21Q50 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated "clock only" jitter attenuator. Figure 1-1 shows this undedicated jitter attenuator as the alternate jitter attenuator.
Clock and Data Jitter Attenuators
The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer depths of either 32 or 128 bits through the LICR. The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuators are shown in Figure 16-6. The jitter attenuators can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. For the jitter attenuator to operate properly, a 2.048MHz clock (50ppm) must be applied at the MCLK pin. On-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIP-P (buffer depth is 128 bits) or 28 UIP-P (buffer depth is 32 bits), the DS21Q50 divides the internal nominal 32.768MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the JALT bit in the receive information register (RIR.5).
Undedicated Clock Jitter Attenuator
The undedicated jitter attenuator prepares a user-supplied clock for use as a transmission clock (TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL or other synthesizers may contain too much jitter to be appropriate for transmission. Network requirements limit the amount of jitter that can be transmitted onto the network. This feature is enabled by setting SC1CR.7 = 1 in transceiver 1.
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Figure 16-5. Jitter Tolerance
1K DS21Q50 Tolerance
40
UNIT INTERVALS (UIpp)
100
10
1.5
1
Minimum Tolerance Level as per ITU G.823 1 10
20
0.2
0.1
100 1K FREQUENCY (Hz)
2.4K
10K
18K
100K
Figure 16-6. Jitter Attenuation
0dB
JITTER ATTENUATION (dB)
ITU G.7XX Prohibited Area
tt e Ji
-20dB
t te rA nu n io at C v ur e
ETS 300 011 & TBR12 Prohibited Area
-40dB
-60dB 1 10
40
100 1K FREQUENCY (Hz)
10K
100K
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17.
CMI (CODE MARK INVERSION)
The DS21Q50 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B-coded signal. Ones are alternately encoded as a logical 1 or 0 level for the full duration of the clock period. Zeros are encoded as a 0-to-1 transition at the middle of the clock period. Figure 17-1 shows an example data pattern and its CMI result. The control bit for enabling CMI is in the OUTAC register as shown below.
Register Name: Register Description: Register Address: Bit Name 7 TTLIE BIT 7 6 OUTAC (Reproduced here for clarity) OUTA Control Register 1A Hex 6 CMII 5 CMIE 4 OA4 3 OA3 2 OA2 FUNCTION TTL Input Enable. When this bit is set, the receiver can accept TTL positive and negative data at the RTIP and RRING inputs. The data is clocked in on the falling edge of MCLK. CMI Invert 0 = CMI input data not inverted 1 = CMI input data inverted Transmit and Receive CMI Enable 0 = Transmit and receive line interface operates in normal AMI/HDB3 mode 1 = Transmit and receive line interface operate in CMI mode. TTIP is CMI output and RTIP is CMI input. In this mode of operation TRING and RRING are no-connects. OUTA Control Bit 4. Inverts OUTA output. OUTA Control Bit 3. See Table 15-1 for details. OUTA Control Bit 2. See Table 15-1for details. OUTA Control Bit 1. See Table 15-1for details. OUTA Control Bit 0. See Table 15-1 for details. 1 OA1 0 OA0
NAME TTLIE CMII
CMIE OA4 OA3 OA2 OA1 OA0
5 4 3 2 1 0
Figure 17-1. CMI Coding
CLOCK DATA CMI
1
1
0
1
0
0
1
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Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMI-coded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the user can also use HDB3 coding. When this register bit is set, the RTIP pin becomes a unipolar CMI input. The CMI signal is processed to extract and align the clock with data. The BPV counts CVs (code violations) in the CMI signal. CVs are defined as consecutive ones of the same polarity as shown in Figure 17-2. If HDB3 precoding is enabled, then the CVs generated by HDB3 are not counted as errors.
Figure 17-2. CMI Code Violation Example
CLOCK DATA CMI
1
1
0
1
0
0
1
CODE VIOLATION
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18.
INTERLEAVED PCM BUS OPERATION
In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data buses to be multiplexed into higher speed data buses, eliminating external hardware, saving board space and cost. The DS21Q50 uses a channel interleave method. See Figure 19-4 and Figure 19-7 for details about the channel interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096MHz bus speed allows two PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to share a common bus. The 16.384MHz bus speed allows eight PCM data streams to share a common bus. See Figure 18-1 for an example of four transceivers sharing a common 8.192MHz PCM bus. The receive elastic stores of each transceiver must be enabled. Through the IBO register, the user can configure each transceiver for a specific bus speed and position. For all IBO bus configurations, each transceiver is assigned an exclusive position in the high-speed PCM bus. When the device is configured for IBO operation, the TSYNCx pin should be configured as an output or as an input connected to ground. The user cannot supply a TSYNCx signal in this mode.
Register Name: Register Description: Register Address: Bit Name NAME -- IBOTCS SCS1 SCS0 IBOEN DA2 DA1 DA0 7 -- IBOR Interleave Bus Operation Register 1C Hex 6 IBOTCS BIT 7 6 5 4 3 2 1 0 5 SCS1 4 SCS0 3 IBOEN 2 DA2 1 DA1 0 DA0
FUNCTION Not Assigned. Should be set to 0. IBO Transmit Clock Source 0 = TCLK pin is the source of transmit clock 1 = transmit clock is internally derived from the clock at the SYSCLK pin System Clock Select Bit 1 (Table 18-2) System Clock Select Bit 0 (Table 18-2) Interleave Bus Operation Enable 0 = interleave bus operation disabled 1 = interleave bus operation enabled Device Assignment Bit 3 (Table 18-1) Device Assignment Bit 2 (Table 18-1) Device Assignment Bit 1 (Table 18-1)
Table 18-1. IBO Device Assignment
DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 FUNCTION 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus
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Table 18-2. IBO System Clock Select
SCS1 0 0 1 1 SCS0 0 1 0 1 FUNCTION 2.048MHz, Single device on bus 4.096MHz, Two devices on bus 8.192MHz, Four devices on bus 16.384MHz, Eight devices on bus
Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines)
Note: See Section 16 for details about the line interface circuit.
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19.
FUNCTIONAL TIMING DIAGRAMS
19.1 Receive Timing Diagrams Figure 19-1. Receive Frame and Multiframe Timing
FRAME# RSYNC 1 RSYNC
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0). NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
Figure 19-2. Receive Boundary Timing (With Elastic Store Disabled)
RCLK
CHANNEL 32
RSER RSYNC
LSB
Si
1
A
CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 2
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Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled)
SYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB MSB
CHANNEL 1
RSER RSYNC1
RSYNC 2
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR.5 = 1).
Figure 19-4. Receive Interleave Bus Operation
RSYNC RSER
1 FR1 CH32
FR2 CH32 FR3 CH32
FR0 CH1
FR0 CH1 FR1 CH1
FR1 CH1
FR2 CH1 FR3 CH1
FR0 CH2
FR0 CH2 FR1 CH2
FR1 CH2
FR2 CH2 FR3 CH2
RSER2
BIT DETAIL SYSCLK RSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 1, CHANNEL 1
LSB
RSER
LSB MSB
NOTE 1: 4.096MHZ BUS CONFIGURATION. NOTE 2: 8.192MHZ BUS CONFIGURATION. NOTE 3: RSYNC IS IN THE INPUT MODE (RCR.5 = 0).
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19.2 Transmit Timing Diagrams Figure 19-5. Transmit Frame and Multiframe Timing
FRAME# TSYNC TSYNC
1
14 15 16 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
9 10
2
NOTE 1: TSYNC IN FRAME MODE (TCR.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR.1 = 1).
Figure 19-6. Transmit Boundary Timing
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB
TSER TSYNC1 TSYNC2
LSB
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0).
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Figure 19-7. Transmit Interleave Bus Operation
TSYNC TSER
1 FR1 CH32 FR0 CH1
FR1 CH1
FR1 CH1
FR2 CH1 FR3 CH1
FR0 CH2
FR0 CH2 FR1 CH2
FR1 CH2
FR2 CH2 FR3 CH2
TSER2
FR2 CH32 FR3 CH32 FR0 CH1
BIT DETAIL SYSCLK TSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 1, CHANNEL 1
LSB
TSER
LSB MSB
NOTE 1: 4.096MHZ BUS CONFIGURATION. NOTE 2: 8.192MHZ BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TCR.0 = 0).
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Figure 19-8. Framer Synchronization Flowchart
P er U ow p
R S=1 LO
FA Search S FA S = 1 SA R S= 1 LO FA S S ync C riteria M et FA SA = 0 S Increm C C ent R 4 S ync C ounter; C C A= 0 R 4S 8m s Tim e O ut CCM R 4 ultifram S e earch (if enabled via C R C 1.0) C C A= 1 R 4S C SM A ultifram S e earch (if enabled via C R C 1.3) C S =1 AS A
R esync if R R =0 C 1.0
CCS R 4 ync C riteria M CC et; R 4SA = 0; R eset C C R4 S ync C ounter
S ync D eclared R S=0 LO
C SS A ync C riteria M et C S A= 0 AS
S FAS C et R (R .1) IR
FA R S esync C riteria M et
C heck for FA S Fram E ing rror (depends on R R C 1.2)
CCR R 4 esync C riteria M et (R .2) IR
C heck for >=915 O of 1000 ut CCW E R 4 ord rrors
If C C is on R4 (C R = 1) C 1.0
C SR A esync C riteria M et; S C SR et A C (R .0) IR
C heck for C S A MW E F ord rror
If C S is on A (C R = 0) C 1.3
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Figure 19-9. Transmit Data Flow
TSER
TAF TNAF.5-7
0
1
Timeslot 0 Pass-Through (TCR.6) 1 Si Bit Insertion Control (TCR.3) CRC4 Multiframe Alignment Word Generation (CCR.4) 0 E-Bit Generation (TCR.5) Receive Side CRC4 Error Detector 1 1 0
Auto Remote Alarm Generation (CCR.4)
TIDR
1 0 Idle Code / Channel Insertion Control via TIR1/2/3/4 0
Code Word Generation 1
CRC4 Enable (CCR.4)
Transmit Unframed All Ones (TCR.4) or Auto AIS (CCR2.5)
AMI or HDB3 Converter CCR.6
To Waveshaping and Line Drivers
KEY:
= Register = Device Pin = Selector
NOTES: 1. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Not Align Frames if the alarm needs to be sent.
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20.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground........................................................................-1.0V to +6.0V Operating Temperature Range for DS21Q50L..........................................................................0C to +70C Operating Temperature Range for DS21Q50LN.....................................................................-40C to +85C Storage Temperature Range.............................................................................................-55C to +125C Soldering Temperature.................................................................See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0C to +70C for DS21Q50L; -40C to +85C for DS21Q50LN.)
PARAMETER Logic 1 Logic 0 Supply (Note 1)
SYMBOL VIH VIL VDD
MIN 2.0 -0.3 3.135
TYP
MAX 5.5 +0.8
UNITS V V V
3.3
3.465
CAPACITANCE
(TA = +25C)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
MIN
TYP 5 7
MAX
UNITS pF pF
DC CHARACTERISTICS
(VDD = 3.3V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3V 5%, TA = -40C to +85C for DS21Q50LN.)
PARAMETER Supply Current at 3.3V (Note 2) Input Leakage (Note 3) Output Leakage (Note 4) Output Current (2.4V) Output Current (0.4V)
Note 1: Note 2: Note 3: Note 4: Applies to RVDD, TVDD, and DVDD.
SYMBOL IDD IIL ILO IOH IOL
MIN -1.0 -1.0 +4.0
TYP 230
MAX +1.0 +1.0
UNITS mA mA mA mA mA
TCLKs = SYSCLKs = MCLK = 2.048MHz; outputs open circuited; TTIPs and TRINGs driving 30W; QRSS data pattern. 0.0V < VIN < VDD. Applied to INT when tri-stated. Applies to output pins in tri-state condition.
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21.
AC TIMING PARAMETERS AND DIAGRAMS
21.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS--MULTIPLEXED PARALLEL PORT
(VDD = 3.3V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3V 5%, TA = -40C to +85C for DS21Q50LN.)
PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall times R/W Hold Time R/W Setup Time before DS High CS Setup Time before DS, WR, or RD Active CS Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE Fall Muxed Address Hold Time Delay Time DS, WR, or RD to AS or ALE Rise Pulse Width AS or ALE High Delay Time, AS or ALE to DS, WR, or RD Output Data Delay Time from DS or RD Data Setup Time
SYMBOL tCYC PWEL PWEH tR , t F tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW
MIN 200 100 100
TYP
MAX
UNITS ns ns ns
20 10 50 20 0 10 0 15 10 20 30 10 20 50 140 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Figure 21-1. Intel Bus Read AC Timing (PBTS = 0)
t CYC ALE t ASD WR
PWASH t ASED PWEH t CS t CH
t ASD PWEL
RD
CS t ASL AD0-AD7 t AHL t DDR t DHR
Figure 21-2. Intel Bus Write Timing (PBTS = 0)
t CYC ALE t ASD RD
PWASH t ASED PWEH t CS t CH
t ASD PWEL
WR
CS t ASL AD0-AD7 t AHL t DSW t DHW
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Figure 21-3. Motorola Bus AC Timing (PBTS = 1)
PWASH AS t ASD DS PWEL t RWS R/W AD0-AD7 (read) t ASL t AHL CS AD0-AD7 (write) t ASL t AHL t DSW t DHW t DDR t CH t DHR t ASED t CYC t RWH PWEH
t CS
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21.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS--NONMULTIPLEXED PARALLEL PORT
(VDD = 3.3V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3V 5%, TA = -40C to +85C for DS21Q50N.)
PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR, or DS Active Delay Time from Either RD or DS Active to Data Valid Hold Time from Either RD, WR, or DS Inactive to CS Inactive Hold Time from CS Inactive to Data Bus ThreeState Wait Time from Either WR or DS Active to Latch Data Data Setup Time to Either WR or DS Inactive Data Hold Time from Either WR or DS Inactive Address Hold from Either WR or DS Inactive
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9
MIN 0 0
TYP
MAX
UNITS ns ns
140 0 5 75 10 10 10 20
ns ns ns ns ns ns ns
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DS21Q50
Figure 21-4. Intel Bus Read Timing (PBTS = 0)
A0-A7 D0-D7
Address Valid Data Valid
5ns (min)/20ns (max)
t5
WR
t1
CS
0ns (min)
0ns (min)
RD
t2
75ns (max)
t3
t4
0ns (min)
Figure 21-5. Intel Bus Write Timing (PBTS = 0)
A0-A7 D0-D7
Address Valid
t7
RD
t8
10ns (min) 10ns (min) t1 0ns min. t2 t6 75ns (min) t4 0ns (min)
CS
0ns (min)
WR
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DS21Q50
Figure 21-6. Motorola Bus Read Timing (PBTS = 1)
A0-A7 D0-D7
Address Valid Data Valid
5ns (min)/20ns (max)
t5
R/W t1
CS
0ns (min) t2 t3 75ns (max) t4 0ns (min)
0ns (min)
DS
Figure 21-7. Motorola Bus Write Timing (PBTS = 1)
A0-A7 D0-D7 10ns (min) R/W t1
CS
Address Valid
t7 t8
10ns (min)
0ns (min) t2 t6 75ns (min) t4 0ns (min)
0ns (min)
DS
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DS21Q50
21.3 Serial Port AC CHARACTERISTICS--SERIAL PORT (BTS1 = 1, BTS0 = 0)
(VDD = 3.3V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3V 5%, TA = -40C to +85C for DS21Q50N.)
PARAMETER Setup Time CS to SCLK Setup Time SDI to SCLK Hold Time SCLK to SDI SCLK High/Low Time SCLK Rise/Fall Time SCLK to CS Inactive CS Inactive Time SCLK to SDO Valid SCLK to SDO Three-State CS Inactive to SDO Three-State
SYMBOL tCSS tSSS tSSH tSLH tSRF tLSC tCM tSSV tSSH tCSH
MIN 50 50 50 200
TYP
MAX
UNITS ns ns ns ns
50 50 250 50 100 100
ns ns ns ns ns ns
Figure 21-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0)
tCM
CS
tCSS tSRF tSLH tLSC
SCLK1 SCLK2 SDI SDO
tSSS LSB
tSSH MSB LSB tSSV HIGH Z LSB MSB tSSH MSB
tCSH
HIGH Z
NOTE 1: OCES =1 AND ICES = 0. NOTE 2: OCES = 0 AND ICES = 1.
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DS21Q50
21.4 Receive AC Characteristics AC CHARACTERISTICS--RECEIVER
(VDD = 3.3.0V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3.0V 5%, TA = -40C to +85C for DS21Q50LN.)
PARAMETER SYSCLK Period (Note 1) SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse Width Delay RCLK to RSER Valid Delay RCLK to RSYNC, OUTA, OUTB Delay SYSCLK to RSER Valid Delay SYSCLK to RSYNC, OUTA, OUTB
Note 1: SYSCLK = 2.048MHz.
SYMBOL tSP tSH tSL tSU tPW tD1 tD2 tD3 tD4
MIN 122 50 50 20 50
TYP 488
MAX
UNITS ns ns
tSH - 5
ns ns
50 50 50 50
ns ns ns ns
Figure 21-9. Receive AC Timing (Receive Elastic Store Disabled)
1
OUTA / OUTB (RCLK) OUTA / OUTB (*RCLK) tD1 RSER
3
MSB of Channel 1
2
tD2
RSYNC
OUTA / OUTB OUTA / OUTB
4
5
NOTE 1: OUTA OR OUTB CONFIGURED TO OUTPUT RCLK (NONINVERTED). NOTE 2: OUTA OR OUTB CONFIGURED TO OUTPUT RCLK (INVERTED). NOTE 3: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 4: OUTA OR OUTB CONFIGURED TO OUTPUT RFSYNC, CRC4 MF SYNC, OR CAS MF SYNC (NONINVERTED). NOTE 5: OUTA OR OUTB CONFIGURED TO OUTPUT RFSYNC, CRC4 MF SYNC, OR CAS MF SYNC (INVERTED).
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DS21Q50
Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled)
t SL
tR
tF
t SH
SYSCLK
t D3 t SP
MSB of Channel 1
RSER RSYNC
1
t D4
OUTA / OUTB 2
t SU t HD
RSYNC
3
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: OUTA OR OUTB CONFIGURED AS CRCR MF SYNC OR CAS MF SYNC. NOTE 3: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 1).
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DS21Q50
21.5 Transmit AC Characteristics AC CHARACTERISTICS--TRANSMIT
(VDD = 3.3V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3V 5%, TA = -40C to +85C for DS21Q50LN.)
PARAMETER TCLK Period TCLK Pulse Width TSYNC Setup to TCLK TSYNC Pulse Width TSER Setup to TCLK Falling TSER Hold from TCLK Falling TCLK Rise and Fall Times
SYMBOL tCP tCH tCL tSU tPW tSU tHD tR, t F
MIN 75 75 20 50 20 20
TYP 488
MAX
UNITS ns ns
tCH - 5 or tSH - 5
ns ns ns ns
25
ns
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DS21Q50
Figure 21-11. Transmit AC Timing (IBO Disabled)
t CP tR tF t CL t CH
TCLK
SU
TSER
t D2
TSYNC1
t SU
t HD
TSYNC 2 OUTA/OUTB 3
t D2
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). NOTE 3: APPLIES TO OUTA AND OUTB WHEN CONFIGURES FOR TPOS AND TNEG OUTPUTS.
Figure 21-12. Transmit AC Timing (IBO Enabled)
t SP tR SYSCLK t SU TSER tF t SL t SH
NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF SYSCLK WHEN THE IBO MODE IS ENABLED.
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DS21Q50
21.6 Special Modes AC Characteristics AC CHARACTERISTICS--SPECIAL MODES
(VDD = 3.3V 5%, TA = 0C to +70C for DS21Q50L; VDD = 3.3V 5%, TA = -40C to +85C for DS21Q50LN.)
PARAMETER RTIP Period RTIP Pulse Width RTIP Setup to RRING Falling TSER Hold from TCLK Falling RTIP, RRING Rise and Fall Times
SYMBOL tCP tCH tCL tSU tHD t R, t F
MIN 75 75 20 20
TYP 488
MAX
UNITS ns ns ns ns ns
25
ns
Special Mode: OUTBC.7 = 1 Note: RTIP and RRING become NRZ data and clock inputs.
Figure 21-13. NRZ Input AC Timing
t CL t CH
tR
tF
RRING
RTIP
t SU
t HD
t CP
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DS21Q50
22.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2004 Maxim Integrated Products * Printed USA
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